Oliver Stannard 9ea2eaeb50 [ARM] Add support for armv7e-m to the .arch directive ...

This will allow compilation of assembly files targeting armv7e-m without having
to specify the Tag_CPU_arch attribute as a workaround.

Differential revision: https://reviews.llvm.org/D40370

Patch by Ian Tessier!

llvm-svn: 319303

2017-11-29 10:12:15 +00:00

..

AArch64

[globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG.

2017-11-28 22:07:05 +00:00

AMDGPU

AMDGPU: Use stricter regexes for add instructions

2017-11-29 02:25:14 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Add support for armv7e-m to the .arch directive

2017-11-29 10:12:15 +00:00

AVR

[AVR] Use the short form of 'clr <reg>'

2017-11-24 15:36:43 +00:00

BPF

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Generic

[CodeGen] Peel off the dominant case in switch statement in lowering

2017-11-14 21:44:09 +00:00

Hexagon

[Hexagon] Make sure to zero-extend bytes before building a vector

2017-11-28 19:13:17 +00:00

Inputs

…

Lanai

MIR: Print the register class or bank in vreg defs

2017-10-24 18:04:54 +00:00

Mips

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

MIR

[mir] Print/Parse both MOLoad and MOStore when they occur together.

2017-11-28 18:57:02 +00:00

MSP430

[DAG] Improve Aliasing of operations to static alloca

2017-07-18 20:06:24 +00:00

Nios2

[Nios2] Target registration

2017-05-29 09:48:30 +00:00

NVPTX

[NVPTX] Implement __nvvm_atom_add_gen_d builtin.

2017-11-07 22:10:54 +00:00

PowerPC

[PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.

2017-11-29 04:09:29 +00:00

RISCV

[RISCV] Use register X0 (ZERO) for constant 0

2017-11-21 08:23:08 +00:00

SPARC

[Sparc] efficient pattern for UINT_TO_FP conversion

2017-11-20 22:33:58 +00:00

SystemZ

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Thumb

[ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb

2017-11-27 10:13:14 +00:00

Thumb2

[arm] Fix Unnecessary reloads from GOT.

2017-11-13 20:45:38 +00:00

WebAssembly

[WebAssembly] Support bitcasted function addresses with varargs.

2017-11-28 17:15:03 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

[X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization.

2017-11-29 00:32:09 +00:00

XCore

[MC] Suppress .Lcfi labels when emitting textual assembly

2017-10-10 00:57:36 +00:00