2d92f7de80
R16-R31 was added into GPRs in https://github.com/llvm/llvm-project/pull/70958, This patch supports the lowering for promoted BMI instructions in EVEX space, enc/dec has been supported in https://github.com/llvm/llvm-project/pull/73899. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
377 lines
16 KiB
TableGen
377 lines
16 KiB
TableGen
//===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the shift and rotate instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Shift/Rotate instructions
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//===----------------------------------------------------------------------===//
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multiclass ShiftRotate<string m, Format RegMRM, Format MemMRM, SDPatternOperator node,
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SchedReadWrite rCL, SchedReadWrite ri, SchedReadWrite mCL,
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SchedReadWrite mi, list<Register> uses = []> {
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let Uses = uses in {
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let isConvertibleToThreeAddress = !if(!eq(m, "shl"), 1, 0) in {
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def 8ri : BinOpRI8U_R<m, RegMRM, Xi8, node>, Sched<[ri]>, DefEFLAGS;
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def 16ri : BinOpRI8U_R<m, RegMRM, Xi16, node>, Sched<[ri]>, DefEFLAGS, OpSize16;
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def 32ri : BinOpRI8U_R<m, RegMRM, Xi32, node>, Sched<[ri]>, DefEFLAGS, OpSize32;
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def 64ri : BinOpRI8U_R<m, RegMRM, Xi64, node>, Sched<[ri]>, DefEFLAGS;
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}
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def 8mi : BinOpMI8U_M<m, MemMRM, Xi8, node>, Sched<[mi, WriteRMW]>, DefEFLAGS;
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def 16mi : BinOpMI8U_M<m, MemMRM, Xi16, node>, Sched<[mi, WriteRMW]>, DefEFLAGS, OpSize16;
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def 32mi : BinOpMI8U_M<m, MemMRM, Xi32, node>, Sched<[mi, WriteRMW]>, DefEFLAGS, OpSize32;
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def 64mi : BinOpMI8U_M<m, MemMRM, Xi64, node>, Sched<[mi, WriteRMW]>, DefEFLAGS, Requires<[In64BitMode]>;
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let SchedRW = [ri] in {
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def 8r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi8, null_frag>;
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def 16r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi16, null_frag>, OpSize16;
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def 32r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi32, null_frag>, OpSize32;
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def 64r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi64, null_frag>;
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}
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let SchedRW = [mi, WriteRMW] in {
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def 8m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi8, null_frag>;
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def 16m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi16, null_frag>, OpSize16;
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def 32m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi32, null_frag>, OpSize32;
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def 64m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi64, null_frag>, Requires<[In64BitMode]>;
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}
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}
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let Uses = !listconcat([CL], uses) in {
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def 8rCL : BinOpRC_R<m, RegMRM, Xi8, node>, Sched<[rCL]>, DefEFLAGS;
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def 16rCL : BinOpRC_R<m, RegMRM, Xi16, node>, Sched<[rCL]>, DefEFLAGS, OpSize16;
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def 32rCL : BinOpRC_R<m, RegMRM, Xi32, node>, Sched<[rCL]>, DefEFLAGS, OpSize32;
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def 64rCL : BinOpRC_R<m, RegMRM, Xi64, node>, Sched<[rCL]>, DefEFLAGS;
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def 8mCL : BinOpMC_M<m, MemMRM, Xi8, node>, Sched<[mCL, WriteRMW]>, DefEFLAGS;
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def 16mCL : BinOpMC_M<m, MemMRM, Xi16, node>, Sched<[mCL, WriteRMW]>, DefEFLAGS, OpSize16;
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def 32mCL : BinOpMC_M<m, MemMRM, Xi32, node>, Sched<[mCL, WriteRMW]>, DefEFLAGS, OpSize32;
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def 64mCL : BinOpMC_M<m, MemMRM, Xi64, node>, Sched<[mCL, WriteRMW]>, DefEFLAGS, Requires<[In64BitMode]>;
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}
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}
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defm SHL: ShiftRotate<"shl", MRM4r, MRM4m, shl, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>;
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defm SHR: ShiftRotate<"shr", MRM5r, MRM5m, srl, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>;
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defm SAR: ShiftRotate<"sar", MRM7r, MRM7m, sra, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>;
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defm ROL: ShiftRotate<"rol", MRM0r, MRM0m, rotl, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd>;
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defm ROR: ShiftRotate<"ror", MRM1r, MRM1m, rotr, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd>;
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defm RCL: ShiftRotate<"rcl", MRM2r, MRM2m, null_frag, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd, [EFLAGS]>;
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defm RCR: ShiftRotate<"rcr", MRM3r, MRM3m, null_frag, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd, [EFLAGS]>;
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// Use the opposite rotate if allows us to use the rotate by 1 instruction.
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def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;
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def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>;
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def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>;
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def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>;
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def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
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def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>;
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def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1 GR32:$src1)>;
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def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1 GR64:$src1)>;
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def : Pat<(store (rotl (loadi8 addr:$dst), (i8 7)), addr:$dst),
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(ROR8m1 addr:$dst)>;
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def : Pat<(store (rotl (loadi16 addr:$dst), (i8 15)), addr:$dst),
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(ROR16m1 addr:$dst)>;
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def : Pat<(store (rotl (loadi32 addr:$dst), (i8 31)), addr:$dst),
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(ROR32m1 addr:$dst)>;
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def : Pat<(store (rotl (loadi64 addr:$dst), (i8 63)), addr:$dst),
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(ROR64m1 addr:$dst)>, Requires<[In64BitMode]>;
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def : Pat<(store (rotr (loadi8 addr:$dst), (i8 7)), addr:$dst),
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(ROL8m1 addr:$dst)>;
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def : Pat<(store (rotr (loadi16 addr:$dst), (i8 15)), addr:$dst),
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(ROL16m1 addr:$dst)>;
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def : Pat<(store (rotr (loadi32 addr:$dst), (i8 31)), addr:$dst),
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(ROL32m1 addr:$dst)>;
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def : Pat<(store (rotr (loadi64 addr:$dst), (i8 63)), addr:$dst),
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(ROL64m1 addr:$dst)>, Requires<[In64BitMode]>;
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// Patterns for rotate with relocImm for the immediate field.
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def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
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(ROL8ri GR8:$src1, relocImm:$src2)>;
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def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),
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(ROL16ri GR16:$src1, relocImm:$src2)>;
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def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)),
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(ROL32ri GR32:$src1, relocImm:$src2)>;
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def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)),
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(ROL64ri GR64:$src1, relocImm:$src2)>;
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def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
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(ROR8ri GR8:$src1, relocImm:$src2)>;
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def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)),
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(ROR16ri GR16:$src1, relocImm:$src2)>;
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def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)),
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(ROR32ri GR32:$src1, relocImm:$src2)>;
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def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)),
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(ROR64ri GR64:$src1, relocImm:$src2)>;
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//===----------------------------------------------------------------------===//
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// Double precision shift instructions (generalizations of rotate)
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//===----------------------------------------------------------------------===//
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class ShlrdOpRRI8U_R<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
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: ITy<o, MRMDestReg, t, (outs t.RegClass:$dst),
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(ins t.RegClass:$src1, t.RegClass:$src2, u8imm:$src3), m, triop_args,
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[]>, NDD<0, TB> {
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let isCommutable = 1;
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let ImmT = Imm8;
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let SchedRW = [WriteSHDrri];
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let Pattern = !if(!eq(m, "shld"),
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[(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, (i8 imm:$src3)))],
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[(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, (i8 imm:$src3)))]);
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}
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class ShlrdOpRRC_R<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
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: BinOpRR<o, m, triop_cl_args, t, (outs t.RegClass:$dst), []>, NDD<0, TB> {
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let Uses = [CL];
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let SchedRW = [WriteSHDrrcl];
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let Pattern = !if(!eq(m, "shld"),
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[(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, CL))],
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[(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, CL))]);
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}
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class ShlrdOpMRI8U_M<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
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: ITy<o, MRMDestMem, t, (outs), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
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m, triop_args, []>, TB {
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let ImmT = Imm8;
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let SchedRW = [WriteSHDmri];
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let mayLoad = 1;
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let mayStore = 1;
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let Pattern = !if(!eq(m, "shld"),
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[(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)), addr:$src1)],
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[(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)), addr:$src1)]);
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}
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class ShlrdOpMRC_M<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
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: BinOpMR<o, m, triop_cl_args, t, (outs), []>, TB {
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let Uses = [CL];
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let SchedRW = [WriteSHDmrcl];
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let mayStore = 1;
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let Pattern = !if(!eq(m, "shld"),
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[(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL), addr:$src1)],
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[(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL), addr:$src1)]);
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}
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multiclass Shlrd<bits<8> o1, bits<8> o2, string m, SDPatternOperator node, SDPatternOperator t_node> {
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def 16rri8 : ShlrdOpRRI8U_R<o1, m, Xi16, t_node>, DefEFLAGS, OpSize16;
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def 32rri8 : ShlrdOpRRI8U_R<o1, m, Xi32, node>, DefEFLAGS, OpSize32;
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def 64rri8 : ShlrdOpRRI8U_R<o1, m, Xi64, node>, DefEFLAGS;
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def 16rrCL : ShlrdOpRRC_R<o2, m, Xi16, t_node>, DefEFLAGS, OpSize16;
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def 32rrCL : ShlrdOpRRC_R<o2, m, Xi32, node>, DefEFLAGS, OpSize32;
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def 64rrCL : ShlrdOpRRC_R<o2, m, Xi64, node>, DefEFLAGS;
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def 16mri8 : ShlrdOpMRI8U_M<o1, m, Xi16, t_node>, DefEFLAGS, OpSize16;
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def 32mri8 : ShlrdOpMRI8U_M<o1, m, Xi32, node>, DefEFLAGS, OpSize32;
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def 64mri8 : ShlrdOpMRI8U_M<o1, m, Xi64, node>, DefEFLAGS;
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def 16mrCL : ShlrdOpMRC_M<o2, m, Xi16, t_node>, DefEFLAGS, OpSize16;
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def 32mrCL : ShlrdOpMRC_M<o2, m, Xi32, node>, DefEFLAGS, OpSize32;
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def 64mrCL : ShlrdOpMRC_M<o2, m, Xi64, node>, DefEFLAGS;
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}
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defm SHLD : Shlrd<0xA4, 0xA5, "shld", fshl, X86fshl>;
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defm SHRD : Shlrd<0xAC, 0xAD, "shrd", fshr, X86fshr>;
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// Sandy Bridge and newer Intel processors support faster rotates using
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// SHLD to avoid a partial flag update on the normal rotate instructions.
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// Use a pseudo so that TwoInstructionPass and register allocation will see
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// this as unary instruction.
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let Predicates = [HasFastSHLDRotate], AddedComplexity = 5,
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Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteSHDrri],
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Constraints = "$src1 = $dst" in {
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def SHLDROT32ri : I<0, Pseudo, (outs GR32:$dst),
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(ins GR32:$src1, u8imm:$shamt), "",
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[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$shamt)))]>;
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def SHLDROT64ri : I<0, Pseudo, (outs GR64:$dst),
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(ins GR64:$src1, u8imm:$shamt), "",
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[(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
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def SHRDROT32ri : I<0, Pseudo, (outs GR32:$dst),
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(ins GR32:$src1, u8imm:$shamt), "",
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[(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$shamt)))]>;
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def SHRDROT64ri : I<0, Pseudo, (outs GR64:$dst),
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(ins GR64:$src1, u8imm:$shamt), "",
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[(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>;
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}
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//===----------------------------------------------------------------------===//
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// BMI Shift/Rotate instructions
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//===----------------------------------------------------------------------===//
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def ROT32L2R_imm8 : SDNodeXForm<imm, [{
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// Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
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return getI8Imm(32 - N->getZExtValue(), SDLoc(N));
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}]>;
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def ROT64L2R_imm8 : SDNodeXForm<imm, [{
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// Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
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return getI8Imm(64 - N->getZExtValue(), SDLoc(N));
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}]>;
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// NOTE: We use WriteShift for these rotates as they avoid the stalls
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// of many of the older x86 rotate instructions.
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class RorXri<X86TypeInfo t>
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: ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
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"rorx", binop_ndd_args, []>, TA, XD, Sched<[WriteShift]> {
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let ImmT = Imm8;
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}
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class RorXmi<X86TypeInfo t>
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: ITy<0xF0, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, u8imm:$src2),
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"rorx", binop_ndd_args, []>, TA, XD, Sched<[WriteShiftLd]> {
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let ImmT = Imm8;
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let mayLoad = 1;
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}
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multiclass RorX<X86TypeInfo t> {
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let Predicates = [HasBMI2, NoEGPR] in {
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def ri : RorXri<t>, VEX;
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def mi : RorXmi<t>, VEX;
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}
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let Predicates = [HasBMI2, HasEGPR, In64BitMode] in {
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def ri_EVEX : RorXri<t>, EVEX;
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def mi_EVEX : RorXmi<t>, EVEX;
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}
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}
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defm RORX32: RorX<Xi32>;
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defm RORX64: RorX<Xi64>;
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class ShiftXrr<string m, X86TypeInfo t>
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: ITy<0xF7, MRMSrcReg4VOp3, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2),
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m, binop_ndd_args, []>, T8, Sched<[WriteShift]>;
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class ShiftXrm<string m, X86TypeInfo t>
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: ITy<0xF7, MRMSrcMem4VOp3, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2),
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m, binop_ndd_args, []>, T8,
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Sched<[WriteShift.Folded,
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// x86memop:$src1
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ReadDefault, ReadDefault, ReadDefault, ReadDefault,
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ReadDefault,
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// RC:$src2
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WriteShift.ReadAfterFold]> {
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let mayLoad = 1;
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}
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multiclass ShiftX<string m, X86TypeInfo t> {
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let Predicates = [HasBMI2, NoEGPR] in {
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def rr : ShiftXrr<m, t>, VEX;
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def rm : ShiftXrm<m, t>, VEX;
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}
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let Predicates = [HasBMI2, HasEGPR, In64BitMode] in {
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def rr_EVEX : ShiftXrr<m, t>, EVEX;
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def rm_EVEX : ShiftXrm<m, t>, EVEX;
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}
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}
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defm SARX32: ShiftX<"sarx", Xi32>, XS;
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defm SARX64: ShiftX<"sarx", Xi64>, XS;
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defm SHRX32: ShiftX<"shrx", Xi32>, XD;
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defm SHRX64: ShiftX<"shrx", Xi64>, XD;
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defm SHLX32: ShiftX<"shlx", Xi32>, PD;
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defm SHLX64: ShiftX<"shlx", Xi64>, PD;
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multiclass RORX_Pats<string suffix> {
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// Prefer RORX which is non-destructive and doesn't update EFLAGS.
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let AddedComplexity = 10 in {
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def : Pat<(rotr GR32:$src, (i8 imm:$shamt)),
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(!cast<Instruction>(RORX32ri#suffix) GR32:$src, imm:$shamt)>;
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def : Pat<(rotr GR64:$src, (i8 imm:$shamt)),
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(!cast<Instruction>(RORX64ri#suffix) GR64:$src, imm:$shamt)>;
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def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
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(!cast<Instruction>(RORX32ri#suffix) GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
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def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
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(!cast<Instruction>(RORX64ri#suffix) GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
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}
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def : Pat<(rotr (loadi32 addr:$src), (i8 imm:$shamt)),
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(!cast<Instruction>(RORX32mi#suffix) addr:$src, imm:$shamt)>;
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def : Pat<(rotr (loadi64 addr:$src), (i8 imm:$shamt)),
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(!cast<Instruction>(RORX64mi#suffix) addr:$src, imm:$shamt)>;
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def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
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(!cast<Instruction>(RORX32mi#suffix) addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
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def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
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(!cast<Instruction>(RORX64mi#suffix) addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
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}
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multiclass ShiftX_Pats<SDNode op, string suffix = ""> {
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// Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
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// immediate shift, i.e. the following code is considered better
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//
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// mov %edi, %esi
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// shl $imm, %esi
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// ... %edi, ...
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//
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// than
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//
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// movb $imm, %sil
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// shlx %sil, %edi, %esi
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// ... %edi, ...
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//
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let AddedComplexity = 1 in {
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def : Pat<(op GR32:$src1, GR8:$src2),
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(!cast<Instruction>(NAME#"32rr"#suffix) GR32:$src1,
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(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(op GR64:$src1, GR8:$src2),
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|
(!cast<Instruction>(NAME#"64rr"#suffix) GR64:$src1,
|
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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|
def : Pat<(op GR32:$src1, (shiftMask32 GR8:$src2)),
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|
(!cast<Instruction>(NAME#"32rr"#suffix) GR32:$src1,
|
|
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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|
def : Pat<(op GR64:$src1, (shiftMask64 GR8:$src2)),
|
|
(!cast<Instruction>(NAME#"64rr"#suffix) GR64:$src1,
|
|
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
|
|
}
|
|
// We prefer to use
|
|
// mov (%ecx), %esi
|
|
// shl $imm, $esi
|
|
//
|
|
// over
|
|
//
|
|
// movb $imm, %al
|
|
// shlx %al, (%ecx), %esi
|
|
//
|
|
// This priority is enforced by IsProfitableToFoldLoad.
|
|
def : Pat<(op (loadi32 addr:$src1), GR8:$src2),
|
|
(!cast<Instruction>(NAME#"32rm"#suffix) addr:$src1,
|
|
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
|
|
def : Pat<(op (loadi64 addr:$src1), GR8:$src2),
|
|
(!cast<Instruction>(NAME#"64rm"#suffix) addr:$src1,
|
|
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
|
|
def : Pat<(op (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
|
|
(!cast<Instruction>(NAME#"32rm"#suffix) addr:$src1,
|
|
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
|
|
def : Pat<(op (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
|
|
(!cast<Instruction>(NAME#"64rm"#suffix) addr:$src1,
|
|
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
|
|
}
|
|
|
|
let Predicates = [HasBMI2, NoEGPR] in {
|
|
defm : RORX_Pats<"">;
|
|
defm SARX : ShiftX_Pats<sra>;
|
|
defm SHRX : ShiftX_Pats<srl>;
|
|
defm SHLX : ShiftX_Pats<shl>;
|
|
}
|
|
|
|
let Predicates = [HasBMI2, HasEGPR] in {
|
|
defm : RORX_Pats<"_EVEX">;
|
|
defm SARX : ShiftX_Pats<sra, "_EVEX">;
|
|
defm SHRX : ShiftX_Pats<srl, "_EVEX">;
|
|
defm SHLX : ShiftX_Pats<shl, "_EVEX">;
|
|
}
|