e0ac46e69d
This reverts commit d618f1c3b12effd0c2bdb7d02108d3551f389d3d. This commit wasn't reviewed ahead of time and significant concerns were raised immediately after it landed. According to our developer policy this warrants immediate revert of the commit. https://llvm.org/docs/DeveloperPolicy.html#patch-reversion-policy Differential Revision: https://reviews.llvm.org/D155509
71 lines
2.6 KiB
C
71 lines
2.6 KiB
C
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=arm64-apple-ios7 | FileCheck %s
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// Memory ordering values.
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enum {
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memory_order_relaxed = 0,
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memory_order_consume = 1,
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memory_order_acquire = 2,
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memory_order_release = 3,
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memory_order_acq_rel = 4,
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memory_order_seq_cst = 5
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};
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typedef struct { void *a, *b; } pointer_pair_t;
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typedef struct { void *a, *b, *c, *d; } pointer_quad_t;
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// rdar://13489679
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extern _Atomic(_Bool) a_bool;
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extern _Atomic(float) a_float;
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extern _Atomic(void*) a_pointer;
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extern _Atomic(pointer_pair_t) a_pointer_pair;
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extern _Atomic(pointer_quad_t) a_pointer_quad;
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// CHECK-LABEL:define{{.*}} void @test0()
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// CHECK: [[TEMP:%.*]] = alloca i8, align 1
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// CHECK-NEXT: store i8 1, ptr [[TEMP]]
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// CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[TEMP]], align 1
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// CHECK-NEXT: store atomic i8 [[T0]], ptr @a_bool seq_cst, align 1
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void test0(void) {
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__c11_atomic_store(&a_bool, 1, memory_order_seq_cst);
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}
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// CHECK-LABEL:define{{.*}} void @test1()
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// CHECK: [[TEMP:%.*]] = alloca float, align 4
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// CHECK-NEXT: store float 3.000000e+00, ptr [[TEMP]]
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// CHECK-NEXT: [[T1:%.*]] = load i32, ptr [[TEMP]], align 4
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// CHECK-NEXT: store atomic i32 [[T1]], ptr @a_float seq_cst, align 4
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void test1(void) {
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__c11_atomic_store(&a_float, 3, memory_order_seq_cst);
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}
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// CHECK-LABEL:define{{.*}} void @test2()
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// CHECK: [[TEMP:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: store ptr @a_bool, ptr [[TEMP]]
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// CHECK-NEXT: [[T1:%.*]] = load i64, ptr [[TEMP]], align 8
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// CHECK-NEXT: store atomic i64 [[T1]], ptr @a_pointer seq_cst, align 8
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void test2(void) {
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__c11_atomic_store(&a_pointer, &a_bool, memory_order_seq_cst);
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}
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// CHECK-LABEL:define{{.*}} void @test3(
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// CHECK: [[PAIR:%.*]] = alloca [[PAIR_T:%.*]], align 8
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// CHECK-NEXT: [[TEMP:%.*]] = alloca [[PAIR_T]], align 8
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// CHECK: llvm.memcpy
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// CHECK-NEXT: [[T1:%.*]] = load i128, ptr [[TEMP]], align 8
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// CHECK-NEXT: store atomic i128 [[T1]], ptr @a_pointer_pair seq_cst, align 16
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void test3(pointer_pair_t pair) {
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__c11_atomic_store(&a_pointer_pair, pair, memory_order_seq_cst);
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}
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// CHECK-LABEL:define{{.*}} void @test4(
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// CHECK-SAME: ptr noundef [[QUAD:%.*]])
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// CHECK: [[QUAD_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[TEMP:%.*]] = alloca [[QUAD_T:%.*]], align 8
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// CHECK-NEXT: store ptr [[QUAD]], ptr [[QUAD_INDIRECT_ADDR]]
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// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TEMP]], ptr align 8 {{%.*}}, i64 32, i1 false)
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// CHECK-NEXT: call void @__atomic_store(i64 noundef 32, ptr noundef @a_pointer_quad, ptr noundef [[TEMP]], i32 noundef 5)
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void test4(pointer_quad_t quad) {
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__c11_atomic_store(&a_pointer_quad, quad, memory_order_seq_cst);
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}
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