a496c8be6e
And dependent commits. Details in D150388. This reverts commit 825b7f0ca5f2211ec3c93139f98d1e24048c225c. This reverts commit 7a98f084c4d121244ef7286bc6503b6a181d446e. This reverts commit b4a62b1fa546312d882fa12dfdcd015177d66826. This reverts commit b7836d856206ec39509d42529f958c920368166b. No conflicts in the code, few tests had conflicts in autogenerated CHECKs: llvm/test/CodeGen/Thumb2/mve-float32regloops.ll llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll Reviewed By: alexfh Differential Revision: https://reviews.llvm.org/D156381
384 lines
14 KiB
LLVM
384 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s | FileCheck -check-prefix=GCN_DBG %s
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define amdgpu_kernel void @test_loop(ptr addrspace(3) %ptr, i32 %n) nounwind {
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; GCN-LABEL: test_loop:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s2, s[0:1], 0xa
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_eq_u32 s2, -1
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; GCN-NEXT: s_cbranch_scc1 .LBB0_3
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; GCN-NEXT: ; %bb.1: ; %for.body.preheader
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_addk_i32 s0, 0x80
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; GCN-NEXT: s_and_b64 vcc, exec, -1
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; GCN-NEXT: s_mov_b32 m0, -1
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; GCN-NEXT: .LBB0_2: ; %for.body
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: ds_read_b32 v1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: ds_write_b32 v0, v1
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; GCN-NEXT: s_add_i32 s0, s0, 4
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; GCN-NEXT: s_mov_b64 vcc, vcc
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; GCN-NEXT: s_cbranch_vccnz .LBB0_2
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; GCN-NEXT: .LBB0_3: ; %for.exit
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; GCN-NEXT: s_endpgm
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;
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; GCN_DBG-LABEL: test_loop:
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; GCN_DBG: ; %bb.0: ; %entry
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; GCN_DBG-NEXT: s_load_dword s0, s[4:5], 0x9
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 0
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; GCN_DBG-NEXT: s_load_dword s1, s[4:5], 0xa
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; GCN_DBG-NEXT: s_mov_b32 s0, 0
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; GCN_DBG-NEXT: s_mov_b32 s2, -1
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: s_cmp_lg_u32 s1, s2
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_cbranch_scc1 .LBB0_2
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; GCN_DBG-NEXT: ; %bb.1: ; %for.exit
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; GCN_DBG-NEXT: s_endpgm
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; GCN_DBG-NEXT: .LBB0_2: ; %for.body
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; GCN_DBG-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN_DBG-NEXT: v_readlane_b32 s0, v0, 1
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; GCN_DBG-NEXT: v_readlane_b32 s2, v0, 0
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; GCN_DBG-NEXT: s_mov_b32 s1, 2
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; GCN_DBG-NEXT: s_lshl_b32 s1, s0, s1
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 s2, 0x80
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_read_b32 v1, v1
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; GCN_DBG-NEXT: s_mov_b32 s2, 1.0
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_add_f32_e64 v2, v1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_write_b32 v1, v2
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; GCN_DBG-NEXT: s_mov_b32 s1, 1
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; GCN_DBG-NEXT: s_add_i32 s0, s0, s1
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; GCN_DBG-NEXT: s_mov_b64 s[2:3], -1
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; GCN_DBG-NEXT: s_and_b64 vcc, exec, s[2:3]
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_cbranch_vccnz .LBB0_2
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; GCN_DBG-NEXT: ; %bb.3: ; %DummyReturnBlock
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; GCN_DBG-NEXT: s_endpgm
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entry:
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%cmp = icmp eq i32 %n, -1
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br i1 %cmp, label %for.exit, label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, ptr addrspace(3) %ptr, i32 %tmp
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%vecload = load float, ptr addrspace(3) %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, ptr addrspace(3) %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br label %for.body
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}
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define amdgpu_kernel void @loop_const_true(ptr addrspace(3) %ptr, i32 %n) nounwind {
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; GCN-LABEL: loop_const_true:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_addk_i32 s0, 0x80
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; GCN-NEXT: s_and_b64 vcc, exec, -1
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; GCN-NEXT: s_mov_b32 m0, -1
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; GCN-NEXT: .LBB1_1: ; %for.body
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: ds_read_b32 v1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: ds_write_b32 v0, v1
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; GCN-NEXT: s_add_i32 s0, s0, 4
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; GCN-NEXT: s_mov_b64 vcc, vcc
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; GCN-NEXT: s_cbranch_vccnz .LBB1_1
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; GCN-NEXT: ; %bb.2: ; %DummyReturnBlock
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; GCN-NEXT: s_endpgm
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;
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; GCN_DBG-LABEL: loop_const_true:
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; GCN_DBG: ; %bb.0: ; %entry
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; GCN_DBG-NEXT: s_load_dword s0, s[4:5], 0x9
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 0
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; GCN_DBG-NEXT: s_mov_b32 s0, 0
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_branch .LBB1_2
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; GCN_DBG-NEXT: .LBB1_1: ; %for.exit
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; GCN_DBG-NEXT: s_endpgm
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; GCN_DBG-NEXT: .LBB1_2: ; %for.body
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; GCN_DBG-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN_DBG-NEXT: v_readlane_b32 s0, v0, 1
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; GCN_DBG-NEXT: v_readlane_b32 s2, v0, 0
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; GCN_DBG-NEXT: s_mov_b32 s1, 2
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; GCN_DBG-NEXT: s_lshl_b32 s1, s0, s1
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 s2, 0x80
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_read_b32 v1, v1
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; GCN_DBG-NEXT: s_mov_b32 s2, 1.0
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_add_f32_e64 v2, v1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_write_b32 v1, v2
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; GCN_DBG-NEXT: s_mov_b32 s1, 1
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; GCN_DBG-NEXT: s_add_i32 s0, s0, s1
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; GCN_DBG-NEXT: s_mov_b64 s[2:3], 0
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; GCN_DBG-NEXT: s_and_b64 vcc, exec, s[2:3]
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_cbranch_vccnz .LBB1_1
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; GCN_DBG-NEXT: s_branch .LBB1_2
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entry:
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br label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, ptr addrspace(3) %ptr, i32 %tmp
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%vecload = load float, ptr addrspace(3) %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, ptr addrspace(3) %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 true, label %for.body, label %for.exit
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}
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define amdgpu_kernel void @loop_const_false(ptr addrspace(3) %ptr, i32 %n) nounwind {
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; GCN-LABEL: loop_const_false:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: s_mov_b32 m0, -1
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; GCN-NEXT: ds_read_b32 v1, v0 offset:128
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: ds_write_b32 v0, v1 offset:128
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; GCN-NEXT: s_endpgm
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;
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; GCN_DBG-LABEL: loop_const_false:
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; GCN_DBG: ; %bb.0: ; %entry
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; GCN_DBG-NEXT: s_load_dword s0, s[4:5], 0x9
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 0
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; GCN_DBG-NEXT: s_mov_b32 s0, 0
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_branch .LBB2_2
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; GCN_DBG-NEXT: .LBB2_1: ; %for.exit
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; GCN_DBG-NEXT: s_endpgm
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; GCN_DBG-NEXT: .LBB2_2: ; %for.body
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; GCN_DBG-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN_DBG-NEXT: v_readlane_b32 s0, v0, 1
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; GCN_DBG-NEXT: v_readlane_b32 s2, v0, 0
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; GCN_DBG-NEXT: s_mov_b32 s1, 2
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; GCN_DBG-NEXT: s_lshl_b32 s1, s0, s1
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 s2, 0x80
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_read_b32 v1, v1
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; GCN_DBG-NEXT: s_mov_b32 s2, 1.0
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_add_f32_e64 v2, v1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_write_b32 v1, v2
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; GCN_DBG-NEXT: s_mov_b32 s1, 1
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; GCN_DBG-NEXT: s_add_i32 s0, s0, s1
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; GCN_DBG-NEXT: s_mov_b64 s[2:3], -1
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; GCN_DBG-NEXT: s_and_b64 vcc, exec, s[2:3]
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_cbranch_vccnz .LBB2_1
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; GCN_DBG-NEXT: s_branch .LBB2_2
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an S_ENDPGM?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, ptr addrspace(3) %ptr, i32 %tmp
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%vecload = load float, ptr addrspace(3) %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, ptr addrspace(3) %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 false, label %for.body, label %for.exit
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}
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define amdgpu_kernel void @loop_const_undef(ptr addrspace(3) %ptr, i32 %n) nounwind {
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; GCN-LABEL: loop_const_undef:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: s_mov_b32 m0, -1
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; GCN-NEXT: ds_read_b32 v1, v0 offset:128
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: ds_write_b32 v0, v1 offset:128
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; GCN-NEXT: s_endpgm
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;
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; GCN_DBG-LABEL: loop_const_undef:
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; GCN_DBG: ; %bb.0: ; %entry
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; GCN_DBG-NEXT: s_load_dword s0, s[4:5], 0x9
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 0
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; GCN_DBG-NEXT: s_mov_b32 s0, 0
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_branch .LBB3_2
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; GCN_DBG-NEXT: .LBB3_1: ; %for.exit
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; GCN_DBG-NEXT: s_endpgm
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; GCN_DBG-NEXT: .LBB3_2: ; %for.body
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; GCN_DBG-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN_DBG-NEXT: v_readlane_b32 s0, v0, 1
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; GCN_DBG-NEXT: v_readlane_b32 s2, v0, 0
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; GCN_DBG-NEXT: s_mov_b32 s1, 2
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; GCN_DBG-NEXT: s_lshl_b32 s1, s0, s1
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 s2, 0x80
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; GCN_DBG-NEXT: s_add_i32 s1, s1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_read_b32 v1, v1
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; GCN_DBG-NEXT: s_mov_b32 s2, 1.0
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; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
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; GCN_DBG-NEXT: v_add_f32_e64 v2, v1, s2
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; GCN_DBG-NEXT: s_mov_b32 m0, -1
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; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
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; GCN_DBG-NEXT: ds_write_b32 v1, v2
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; GCN_DBG-NEXT: s_mov_b32 s1, 1
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; GCN_DBG-NEXT: s_add_i32 s0, s0, s1
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; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
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; GCN_DBG-NEXT: s_cbranch_scc1 .LBB3_1
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; GCN_DBG-NEXT: s_branch .LBB3_2
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an s_endpgm?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, ptr addrspace(3) %ptr, i32 %tmp
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%vecload = load float, ptr addrspace(3) %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, ptr addrspace(3) %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 undef, label %for.body, label %for.exit
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}
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define amdgpu_kernel void @loop_arg_0(ptr addrspace(3) %ptr, i32 %n) nounwind {
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; GCN-LABEL: loop_arg_0:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_mov_b32 m0, -1
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; GCN-NEXT: ds_read_u8 v0, v0
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; GCN-NEXT: s_load_dword s4, s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s0, v0
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; GCN-NEXT: s_bitcmp1_b32 s0, 0
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; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
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; GCN-NEXT: s_xor_b64 s[2:3], s[0:1], -1
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; GCN-NEXT: s_add_i32 s0, s4, 0x80
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; GCN-NEXT: s_and_b64 vcc, exec, s[2:3]
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; GCN-NEXT: .LBB4_1: ; %for.body
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: ds_read_b32 v1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: ds_write_b32 v0, v1
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; GCN-NEXT: s_add_i32 s0, s0, 4
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; GCN-NEXT: s_mov_b64 vcc, vcc
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; GCN-NEXT: s_cbranch_vccz .LBB4_1
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; GCN-NEXT: ; %bb.2: ; %for.exit
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; GCN-NEXT: s_endpgm
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;
|
|
; GCN_DBG-LABEL: loop_arg_0:
|
|
; GCN_DBG: ; %bb.0: ; %entry
|
|
; GCN_DBG-NEXT: s_load_dword s0, s[4:5], 0x9
|
|
; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 0
|
|
; GCN_DBG-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN_DBG-NEXT: s_mov_b32 m0, -1
|
|
; GCN_DBG-NEXT: ds_read_u8 v1, v1
|
|
; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN_DBG-NEXT: v_readfirstlane_b32 s0, v1
|
|
; GCN_DBG-NEXT: s_and_b32 s0, 1, s0
|
|
; GCN_DBG-NEXT: s_cmp_eq_u32 s0, 1
|
|
; GCN_DBG-NEXT: s_cselect_b64 s[0:1], -1, 0
|
|
; GCN_DBG-NEXT: s_mov_b64 s[2:3], -1
|
|
; GCN_DBG-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
|
|
; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 1
|
|
; GCN_DBG-NEXT: v_writelane_b32 v0, s1, 2
|
|
; GCN_DBG-NEXT: s_mov_b32 s0, 0
|
|
; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 3
|
|
; GCN_DBG-NEXT: s_branch .LBB4_2
|
|
; GCN_DBG-NEXT: .LBB4_1: ; %for.exit
|
|
; GCN_DBG-NEXT: s_endpgm
|
|
; GCN_DBG-NEXT: .LBB4_2: ; %for.body
|
|
; GCN_DBG-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN_DBG-NEXT: v_readlane_b32 s0, v0, 3
|
|
; GCN_DBG-NEXT: v_readlane_b32 s2, v0, 1
|
|
; GCN_DBG-NEXT: v_readlane_b32 s3, v0, 2
|
|
; GCN_DBG-NEXT: v_readlane_b32 s4, v0, 0
|
|
; GCN_DBG-NEXT: s_mov_b32 s1, 2
|
|
; GCN_DBG-NEXT: s_lshl_b32 s1, s0, s1
|
|
; GCN_DBG-NEXT: s_add_i32 s1, s1, s4
|
|
; GCN_DBG-NEXT: s_mov_b32 s4, 0x80
|
|
; GCN_DBG-NEXT: s_add_i32 s1, s1, s4
|
|
; GCN_DBG-NEXT: s_mov_b32 m0, -1
|
|
; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
|
|
; GCN_DBG-NEXT: ds_read_b32 v1, v1
|
|
; GCN_DBG-NEXT: s_mov_b32 s4, 1.0
|
|
; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN_DBG-NEXT: v_add_f32_e64 v2, v1, s4
|
|
; GCN_DBG-NEXT: s_mov_b32 m0, -1
|
|
; GCN_DBG-NEXT: v_mov_b32_e32 v1, s1
|
|
; GCN_DBG-NEXT: ds_write_b32 v1, v2
|
|
; GCN_DBG-NEXT: s_mov_b32 s1, 1
|
|
; GCN_DBG-NEXT: s_add_i32 s0, s0, s1
|
|
; GCN_DBG-NEXT: s_and_b64 vcc, exec, s[2:3]
|
|
; GCN_DBG-NEXT: v_writelane_b32 v0, s0, 3
|
|
; GCN_DBG-NEXT: s_cbranch_vccnz .LBB4_1
|
|
; GCN_DBG-NEXT: s_branch .LBB4_2
|
|
entry:
|
|
%cond = load volatile i1, ptr addrspace(3) null
|
|
br label %for.body
|
|
|
|
for.exit:
|
|
ret void
|
|
|
|
for.body:
|
|
%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
|
%tmp = add i32 %indvar, 32
|
|
%arrayidx = getelementptr float, ptr addrspace(3) %ptr, i32 %tmp
|
|
%vecload = load float, ptr addrspace(3) %arrayidx, align 4
|
|
%add = fadd float %vecload, 1.0
|
|
store float %add, ptr addrspace(3) %arrayidx, align 8
|
|
%inc = add i32 %indvar, 1
|
|
br i1 %cond, label %for.body, label %for.exit
|
|
}
|