8ea72b3887
VLST return values are coerced to VLATs in the function epilog for consistency with the VLAT ABI. Previously, this coercion was done through memory. It is preferable to use the llvm.experimental.vector.insert intrinsic to avoid going through memory here. Reviewed By: c-rhodes Differential Revision: https://reviews.llvm.org/D94290
80 lines
5.0 KiB
C++
80 lines
5.0 KiB
C++
// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=128 | FileCheck %s -D#VBITS=128 --check-prefixes=CHECK,CHECK128
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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=256 | FileCheck %s -D#VBITS=256 --check-prefixes=CHECK,CHECKWIDE
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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=512 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECKWIDE
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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=1024 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECKWIDE
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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=2048 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECKWIDE
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// REQUIRES: aarch64-registered-target
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// Examples taken from section "3.7.3.3 Behavior specific to SVE
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// vectors" of the SVE ACLE (Version 00bet6) that can be found at
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// https://developer.arm.com/documentation/100987/latest
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//
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// Example has been expanded to work with mutiple values of
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// -msve-vector-bits.
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#include <arm_sve.h>
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// Page 26, first paragraph of 3.7.3.3: sizeof and alignof
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#if __ARM_FEATURE_SVE_BITS
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#define N __ARM_FEATURE_SVE_BITS
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typedef svfloat32_t fixed_svfloat __attribute__((arm_sve_vector_bits(N)));
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void test01() {
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static_assert(alignof(fixed_svfloat) == 16,
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"Invalid align of Vector Length Specific Type.");
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static_assert(sizeof(fixed_svfloat) == N / 8,
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"Invalid size of Vector Length Specific Type.");
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}
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#endif
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// Page 26, items 1 and 2 of 3.7.3.3: how VLST and GNUT are related.
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#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
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#define N __ARM_FEATURE_SVE_BITS
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typedef svfloat64_t fixed_svfloat64 __attribute__((arm_sve_vector_bits(N)));
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typedef float64_t gnufloat64 __attribute__((vector_size(N / 8)));
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void test02() {
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static_assert(alignof(fixed_svfloat64) == alignof(gnufloat64),
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"Align of Vector Length Specific Type and GNU Vector Types "
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"should be the same.");
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static_assert(sizeof(fixed_svfloat64) == sizeof(gnufloat64),
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"Size of Vector Length Specific Type and GNU Vector Types "
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"should be the same.");
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}
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#endif
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// Page 27, item 1.
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#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
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#define N __ARM_FEATURE_SVE_BITS
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// CHECK-LABEL: define{{.*}} <vscale x 4 x i32> @_Z1f9__SVE_VLSIu11__SVInt32_tLj
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// CHECK-SAME: [[#VBITS]]
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// CHECK-SAME: EES_(<vscale x 4 x i32> %x.coerce, <vscale x 4 x i32> %y.coerce)
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE:%.*]], i64 0)
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// CHECK-NEXT: [[Y:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE1:%.*]], i64 0)
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// CHECK-NEXT: [[ADD:%.*]] = add <[[#div(VBITS, 32)]] x i32> [[Y]], [[X]]
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// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v[[#div(VBITS, 32)]]i32(<vscale x 4 x i32> undef, <[[#div(VBITS, 32)]] x i32> [[ADD]], i64 0)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
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typedef svint32_t vec __attribute__((arm_sve_vector_bits(N)));
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auto f(vec x, vec y) { return x + y; } // Returns a vec.
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#endif
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// Page 27, item 3, adapted for a generic value of __ARM_FEATURE_SVE_BITS
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#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
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#define N __ARM_FEATURE_SVE_BITS
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typedef int16_t vec1 __attribute__((vector_size(N / 8)));
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void f(vec1);
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typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N)));
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// CHECK-LABEL: define{{.*}} void @_Z1g9__SVE_VLSIu11__SVInt16_tLj
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// CHECK-SAME: [[#VBITS]]
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// CHECK-SAME: EE(<vscale x 8 x i16> %x.coerce)
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// CHECK-NEXT: entry:
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// CHECK128-NEXT: [[X:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0)
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// CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> [[X]]) [[ATTR5:#.*]]
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// CHECK128-NEXT: ret void
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// CHECKWIDE-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS, 16)]] x i16>, align 16
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// CHECKWIDE-NEXT: [[X:%.*]] = call <[[#div(VBITS, 16)]] x i16> @llvm.experimental.vector.extract.v[[#div(VBITS, 16)]]i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0)
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// CHECKWIDE-NEXT: store <[[#div(VBITS, 16)]] x i16> [[X]], <[[#div(VBITS, 16)]] x i16>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6:!tbaa !.*]]
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// CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]
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// CHECKWIDE-NEXT: ret void
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void g(vec2 x) { f(x); } // OK
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#endif
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