78ccb0359d
These cause problems for later optimizations, just using an unused vreg like SelectionDAG generates better code in the end, and obviates the need for some GISel specific flag optimizations. Differential Revision: https://reviews.llvm.org/D89419
111 lines
3.7 KiB
YAML
111 lines
3.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64--- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s
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---
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name: test_loop_phi_fpr_to_gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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liveins: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: test_loop_phi_fpr_to_gpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
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; CHECK: bb.2:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
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; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK: STRHHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)
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; CHECK: B %bb.2
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bb.0:
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successors: %bb.1(0x80000000)
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%0:gpr(s1) = G_IMPLICIT_DEF
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%4:gpr(p0) = G_IMPLICIT_DEF
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%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
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bb.1:
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successors: %bb.2(0x80000000)
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%6:gpr(s32) = G_IMPLICIT_DEF
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%7:gpr(s32) = G_SELECT %0(s1), %6, %6
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%1:gpr(s16) = G_TRUNC %7(s32)
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bb.2:
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successors: %bb.2(0x80000000)
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%3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
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%5:fpr(s16) = G_FPTRUNC %8(s32)
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G_STORE %3(s16), %4(p0) :: (store 2 into `half* undef`)
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G_BR %bb.2
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...
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---
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name: test_loop_phi_gpr_to_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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liveins: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: test_loop_phi_gpr_to_fpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
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; CHECK: bb.2:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
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; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
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; CHECK: STRHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)
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; CHECK: B %bb.2
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bb.0:
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successors: %bb.1(0x80000000)
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%0:gpr(s1) = G_IMPLICIT_DEF
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%4:gpr(p0) = G_IMPLICIT_DEF
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%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
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bb.1:
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successors: %bb.2(0x80000000)
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%6:gpr(s32) = G_IMPLICIT_DEF
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%7:gpr(s32) = G_SELECT %0(s1), %6, %6
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%1:gpr(s16) = G_TRUNC %7(s32)
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bb.2:
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successors: %bb.2(0x80000000)
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%3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
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%5:fpr(s16) = G_FPTRUNC %8(s32)
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G_STORE %3(s16), %4(p0) :: (store 2 into `half* undef`)
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G_BR %bb.2
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...
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