fceadbcb33
There's more smarts in AArch64ISelLowering that we don't have yet, but this change incrementally improves some of the more common patterns. I think future iterations will want to use some combination of PostLegalizerCombiner and the selector to catch the other cases. Differential Revision: https://reviews.llvm.org/D82340
150 lines
4.6 KiB
YAML
150 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_constant_vec_pool_v2f64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: test_constant_vec_pool_v2f64
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
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; CHECK: RET_ReallyLR
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%0:gpr(p0) = COPY $x0
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%3:fpr(s64) = G_FCONSTANT double 5.000000e-01
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%2:fpr(s64) = G_FCONSTANT double 1.600000e+01
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%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
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G_STORE %1(<2 x s64>), %0(p0) :: (store 16)
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RET_ReallyLR
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...
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---
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name: test_constant_vec_pool_v4f32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 1
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: test_constant_vec_pool_v4f32
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
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; CHECK: RET_ReallyLR
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%0:gpr(p0) = COPY $x0
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%3:fpr(s32) = G_FCONSTANT float 5.000000e-01
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%2:fpr(s32) = G_FCONSTANT float 1.600000e+01
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%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %3(s32), %3(s32)
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G_STORE %1(<4 x s32>), %0(p0) :: (store 16)
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RET_ReallyLR
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...
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---
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name: test_constant_vec_pool_v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 1
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: test_constant_vec_pool_v2i64
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
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; CHECK: RET_ReallyLR
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%0:gpr(p0) = COPY $x0
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%3:gpr(s64) = G_CONSTANT i64 67839
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%2:gpr(s64) = G_CONSTANT i64 12375
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%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
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G_STORE %1(<2 x s64>), %0(p0) :: (store 16)
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RET_ReallyLR
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...
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---
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name: test_constant_vec_pool_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 1
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: test_constant_vec_pool_v4i32
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
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; CHECK: RET_ReallyLR
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%0:gpr(p0) = COPY $x0
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%3:gpr(s32) = G_CONSTANT i32 67839
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%2:gpr(s32) = G_CONSTANT i32 12375
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%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %2(s32), %3(s32)
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G_STORE %1(<4 x s32>), %0(p0) :: (store 16)
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RET_ReallyLR
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...
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---
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name: test_constant_vec_pool_v2i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 1
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: test_constant_vec_pool_v2i32
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: STRDui [[LDRDui]], [[COPY]], 0 :: (store 8)
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; CHECK: RET_ReallyLR
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%0:gpr(p0) = COPY $x0
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%3:gpr(s32) = G_CONSTANT i32 67839
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%2:gpr(s32) = G_CONSTANT i32 12375
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%1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32)
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G_STORE %1(<2 x s32>), %0(p0) :: (store 8)
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RET_ReallyLR
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...
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