511f7f5785
We need to be able to load and store s128 for memcpy inlining, where we want to generate Q register mem ops. Making these legal also requires that we add some support in other instructions. Regbankselect should also know about these since they have no GPR register class that can hold them, so need special handling to live on the FPR bank. Differential Revision: https://reviews.llvm.org/D65166 llvm-svn: 366857
29 lines
885 B
YAML
29 lines
885 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select %s -o - | FileCheck %s
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...
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---
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name: extract_64_128
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: extract_64_128
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1
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; CHECK: $d3 = COPY [[COPY1]]
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; CHECK: $d4 = COPY [[CPYi64_]]
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; CHECK: RET_ReallyLR implicit $d3
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%0:fpr(s128) = COPY $q0
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%2:fpr(s64) = G_EXTRACT %0(s128), 0
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%3:fpr(s64) = G_EXTRACT %0(s128), 64
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$d3 = COPY %2(s64)
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$d4 = COPY %3(s64)
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RET_ReallyLR implicit $d3
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...
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