5cdf6ed744
Recently a few patches are made to move towards using select i1 instead of and/or i1 to represent "a && b"/"a || b" in C/C++. "a && b" in C/C++ does not evaluate b if a is false whereas 'and a, b' in IR evaluates b and uses its result regardless of the result of a. This is problematic because it can cause miscompilation if b was an erroneous operation (https://llvm.org/pr48353). In C/C++, the result is simply false because b is not evaluated, but in IR the result is poison. The discussion at D93065 has more context about this. This patch makes two branch-splitting optimizations (one in SelectionDAGBuilder, one in CodeGenPrepare) recognize select form of and/or as well using m_LogicalAnd/Or. Since it is CodeGen, I think this is semantically ok (at least as safe as what codegen already did). Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93853
127 lines
2.6 KiB
LLVM
127 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: test_or
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; CHECK: cbnz w0, {{LBB[0-9]+_2}}
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; CHECK: cbz w1, {{LBB[0-9]+_1}}
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define i64 @test_or(i32 %a, i32 %b) {
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bb1:
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%0 = icmp eq i32 %a, 0
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%1 = icmp eq i32 %b, 0
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%or.cond = or i1 %0, %1
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br i1 %or.cond, label %bb3, label %bb4, !prof !0
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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; CHECK-LABEL: test_or_select
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; CHECK: cbnz w0, {{LBB[0-9]+_2}}
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; CHECK: cbz w1, {{LBB[0-9]+_1}}
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define i64 @test_or_select(i32 %a, i32 %b) {
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bb1:
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%0 = icmp eq i32 %a, 0
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%1 = icmp eq i32 %b, 0
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%or.cond = select i1 %0, i1 true, i1 %1
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br i1 %or.cond, label %bb3, label %bb4, !prof !0
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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; CHECK-LABEL: test_and
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; CHECK: cbnz w0, {{LBB[0-9]+_2}}
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; CHECK: cbz w1, {{LBB[0-9]+_1}}
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define i64 @test_and(i32 %a, i32 %b) {
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bb1:
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%0 = icmp ne i32 %a, 0
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%1 = icmp ne i32 %b, 0
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%or.cond = and i1 %0, %1
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br i1 %or.cond, label %bb4, label %bb3, !prof !1
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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; CHECK-LABEL: test_and_select
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; CHECK: cbnz w0, {{LBB[0-9]+_2}}
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; CHECK: cbz w1, {{LBB[0-9]+_1}}
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define i64 @test_and_select(i32 %a, i32 %b) {
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bb1:
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%0 = icmp ne i32 %a, 0
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%1 = icmp ne i32 %b, 0
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%or.cond = select i1 %0, i1 %1, i1 false
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br i1 %or.cond, label %bb4, label %bb3, !prof !1
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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; If the branch is unpredictable, don't add another branch.
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; CHECK-LABEL: test_or_unpredictable
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; CHECK: cmp w0, #0
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: cmp w1, #0
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; CHECK-NEXT: cset w9, eq
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: tbnz w8, #0,
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define i64 @test_or_unpredictable(i32 %a, i32 %b) {
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bb1:
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%0 = icmp eq i32 %a, 0
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%1 = icmp eq i32 %b, 0
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%or.cond = or i1 %0, %1
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br i1 %or.cond, label %bb3, label %bb4, !unpredictable !2
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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; CHECK-LABEL: test_and_unpredictable
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; CHECK: cmp w0, #0
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; CHECK-NEXT: cset w8, ne
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; CHECK-NEXT: cmp w1, #0
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; CHECK-NEXT: cset w9, ne
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: tbz w8, #0,
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define i64 @test_and_unpredictable(i32 %a, i32 %b) {
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bb1:
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%0 = icmp ne i32 %a, 0
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%1 = icmp ne i32 %b, 0
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%or.cond = and i1 %0, %1
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br i1 %or.cond, label %bb4, label %bb3, !unpredictable !2
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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declare i64 @bar()
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!0 = !{!"branch_weights", i32 5128, i32 32}
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!1 = !{!"branch_weights", i32 1024, i32 4136}
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!2 = !{}
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