21bfd068b3
Add the aarch64[_be]-*-gnu_ilp32 targets to support the GNU ILP32 ABI for AArch64. The needed codegen changes were mostly already implemented in D61259, which added support for the watchOS ILP32 ABI. The main changes are: - Wiring up the new target to enable ILP32 codegen and MC. - ILP32 va_list support. - ILP32 TLSDESC relocation support. There was existing MC support for ELF ILP32 relocations from D25159 which could be enabled by passing "-target-abi ilp32" to llvm-mc. This was changed to check for "gnu_ilp32" in the target triple instead. This shouldn't cause any issues since the existing support was slightly broken: it was generating ELF64 objects instead of the ELF32 object files expected by the GNU ILP32 toolchain. This target has been tested by running the full rustc testsuite on a big-endian ILP32 system based on the GCC ILP32 toolchain. Reviewed By: kristof.beyls Differential Revision: https://reviews.llvm.org/D94143
143 lines
4.1 KiB
LLVM
143 lines
4.1 KiB
LLVM
; RUN: llc -aarch64-load-store-renaming=true -verify-machineinstrs -mtriple=arm64-linux-gnu_ilp32 -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s
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%va_list = type {i8*, i8*, i8*, i32, i32}
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@var = dso_local global %va_list zeroinitializer, align 8
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declare void @llvm.va_start(i8*)
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define dso_local void @test_simple(i32 %n, ...) {
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; CHECK-LABEL: test_simple:
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; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
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; CHECK: add x[[STACK_TOP:[0-9]+]], sp, #[[STACKSIZE]]
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; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
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; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
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; CHECK-DAG: stp x6, x7, [sp, #
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; ... omit middle ones ...
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; CHECK-DAG: str x1, [sp, #[[GR_BASE:[0-9]+]]]
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; CHECK-DAG: stp q0, q1, [sp]
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; ... omit middle ones ...
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; CHECK-DAG: stp q6, q7, [sp, #
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; CHECK: str w[[STACK_TOP]], [x[[VA_LIST]]]
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; CHECK: add x[[GR_TOPTMP:[0-9]+]], sp, #[[GR_BASE]]
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; CHECK: add [[GR_TOP:w[0-9]+]], w[[GR_TOPTMP]], #56
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; CHECK: mov x[[VR_TOPTMP:[0-9]+]], sp
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; CHECK: add [[VR_TOP:w[0-9]+]], w[[VR_TOPTMP]], #128
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; CHECK: stp [[GR_TOP]], [[VR_TOP]], [x[[VA_LIST]], #4]
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; CHECK: mov [[GRVR:x[0-9]+]], #-56
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; CHECK: movk [[GRVR]], #65408, lsl #32
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; CHECK: stur [[GRVR]], [x[[VA_LIST]], #12]
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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ret void
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}
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define dso_local void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
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; CHECK-LABEL: test_fewargs:
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; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
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; CHECK: add x[[STACK_TOP:[0-9]+]], sp, #[[STACKSIZE]]
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; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
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; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
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; CHECK-DAG: stp x6, x7, [sp, #
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; ... omit middle ones ...
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; CHECK-DAG: str x3, [sp, #[[GR_BASE:[0-9]+]]]
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; CHECK-DAG: stp q6, q7, [sp, #80]
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; ... omit middle ones ...
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; CHECK-DAG: str q1, [sp]
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; CHECK: str w[[STACK_TOP]], [x[[VA_LIST]]]
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; CHECK: add x[[GR_TOPTMP:[0-9]+]], sp, #[[GR_BASE]]
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; CHECK: add [[GR_TOP:w[0-9]+]], w[[GR_TOPTMP]], #40
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; CHECK: mov x[[VR_TOPTMP:[0-9]+]], sp
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; CHECK: add [[VR_TOP:w[0-9]+]], w[[VR_TOPTMP]], #112
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; CHECK: stp [[GR_TOP]], [[VR_TOP]], [x[[VA_LIST]], #4]
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; CHECK: mov [[GRVR_OFFS:x[0-9]+]], #-40
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; CHECK: movk [[GRVR_OFFS]], #65424, lsl #32
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; CHECK: stur [[GRVR_OFFS]], [x[[VA_LIST]], #12]
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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ret void
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}
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define dso_local void @test_nospare([8 x i64], [8 x float], ...) {
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; CHECK-LABEL: test_nospare:
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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; CHECK-NOT: sub sp, sp
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; CHECK: mov x[[STACK:[0-9]+]], sp
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; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var
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; CHECK: str w[[STACK]], [x[[VAR]]]
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ret void
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}
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; If there are non-variadic arguments on the stack (here two i64s) then the
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; __stack field should point just past them.
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define dso_local void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) {
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; CHECK-LABEL: test_offsetstack:
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; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #48]
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; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16]
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; CHECK-DAG: str {{q[0-9]+}}, [sp]
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; CHECK-DAG: add x[[STACK_TOP:[0-9]+]], sp, #96
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; CHECK-DAG: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var
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; CHECK-DAG: str w[[STACK_TOP]], [x[[VAR]]]
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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ret void
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}
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declare void @llvm.va_end(i8*)
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define dso_local void @test_va_end() nounwind {
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; CHECK-LABEL: test_va_end:
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; CHECK-NEXT: %bb.0
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_end(i8* %addr)
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ret void
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; CHECK-NEXT: ret
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}
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declare void @llvm.va_copy(i8* %dest, i8* %src)
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@second_list = dso_local global %va_list zeroinitializer
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define dso_local void @test_va_copy() {
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; CHECK-LABEL: test_va_copy:
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%srcaddr = bitcast %va_list* @var to i8*
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%dstaddr = bitcast %va_list* @second_list to i8*
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call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
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; CHECK: add x[[SRC:[0-9]+]], {{x[0-9]+}}, :lo12:var
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; CHECK: ldr [[BLOCK:q[0-9]+]], [x[[SRC]]]
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; CHECK: add x[[DST:[0-9]+]], {{x[0-9]+}}, :lo12:second_list
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; CHECK: ldr [[BLOCK:w[0-9]+]], [x[[SRC]], #16]
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; CHECK: str [[BLOCK:q[0-9]+]], [x[[DST]]]
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; CHECK: str [[BLOCK:w[0-9]+]], [x[[DST]], #16]
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ret void
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; CHECK: ret
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}
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