eba6deab22
CTLZ and CTPOP are lowered to CLZ and CNT instructions respectively. CTTZ is not a native SVE operation but is instead lowered to: CTTZ(V) => CTLZ(BITREVERSE(V)) In the case of fixed-length support using SVE we also lower CTTZ operating on NEON sized vectors because of its reliance on BITREVERSE which is also lowered to SVE intructions at these lengths. Differential Revision: https://reviews.llvm.org/D93607
174 lines
5.0 KiB
LLVM
174 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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target triple = "aarch64-unknown-linux-gnu"
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;
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; CLZ
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;
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define <vscale x 16 x i8> @ctlz_b(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: ctlz_b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: clz z0.b, p0/m, z0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @ctlz_h(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: ctlz_h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: clz z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16> %a)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @ctlz_s(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: ctlz_s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: clz z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> %a)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @ctlz_d(<vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: ctlz_d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: clz z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.ctlz.nxv2i64(<vscale x 2 x i64> %a)
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ret <vscale x 2 x i64> %res
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}
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;
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; CNT
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;
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define <vscale x 16 x i8> @ctpop_b(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: ctpop_b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cnt z0.b, p0/m, z0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.ctpop.nxv16i8(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @ctpop_h(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: ctpop_h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: cnt z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.ctpop.nxv8i16(<vscale x 8 x i16> %a)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @ctpop_s(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: ctpop_s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: cnt z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.ctpop.nxv4i32(<vscale x 4 x i32> %a)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @ctpop_d(<vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: ctpop_d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: cnt z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.ctpop.nxv2i64(<vscale x 2 x i64> %a)
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ret <vscale x 2 x i64> %res
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}
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;
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; Count trailing zeros
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;
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define <vscale x 16 x i8> @cttz_b(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: cttz_b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: rbit z0.b, p0/m, z0.b
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; CHECK-NEXT: clz z0.b, p0/m, z0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @cttz_h(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: cttz_h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: rbit z0.h, p0/m, z0.h
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; CHECK-NEXT: clz z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %a)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @cttz_s(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: cttz_s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: rbit z0.s, p0/m, z0.s
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; CHECK-NEXT: clz z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %a)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @cttz_d(<vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: cttz_d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: rbit z0.d, p0/m, z0.d
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; CHECK-NEXT: clz z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %a)
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ret <vscale x 2 x i64> %res
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}
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attributes #0 = { "target-features"="+sve" }
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declare <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.ctlz.nxv2i64(<vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.ctpop.nxv16i8(<vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.ctpop.nxv8i16(<vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.ctpop.nxv4i32(<vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.ctpop.nxv2i64(<vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>)
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