314e29ed2b
Previously, instructions which could be expressed as VOP3 in addition to another encoding had a _e64 suffix on the tablegen record name, while those only available as VOP3 did not. With this patch, all VOP3s will have the _e64 suffix. The assembly does not change, only the mir. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D94341 Change-Id: Ia8ec8890d47f8f94bbbdac43745b4e9dd2b03423
29 lines
1.4 KiB
YAML
29 lines
1.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
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---
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name: bswap_i32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX7-LABEL: name: bswap_i32_vv
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[V_ALIGNBIT_B32_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY]], 8, implicit $exec
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; GFX7: [[V_ALIGNBIT_B32_e64_1:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY]], 24, implicit $exec
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; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16711935
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; GFX7: [[V_BFI_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFI_B32_e64 [[S_MOV_B32_]], [[V_ALIGNBIT_B32_e64_1]], [[V_ALIGNBIT_B32_e64_]], implicit $exec
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; GFX7: S_ENDPGM 0, implicit [[V_BFI_B32_e64_]]
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; GFX8-LABEL: name: bswap_i32_vv
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
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; GFX8: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_BSWAP %0
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S_ENDPGM 0, implicit %1
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...
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