7a880ab388
Exec mask manipulation inserted by SIWholeQuadMode barriers to instruction scheduling. Move the entire pass after the machine instruction scheduler and make changes so pass is correct for non-SSA operation. These changes should leave the pass still usable pre-scheduler, although tests have be updated to reflect post-scheduler results. Reviewed By: nhaehnle Differential Revision: https://reviews.llvm.org/D88081
191 lines
7.6 KiB
LLVM
191 lines
7.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CHECK %s
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; Check that WQM is not triggered by the softwqm intrinsic alone.
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;
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;CHECK-LABEL: {{^}}test1:
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;CHECK-NOT: s_wqm_b64 exec, exec
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;CHECK: buffer_load_dword
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;CHECK: buffer_load_dword
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;CHECK: v_add_f32_e32
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define amdgpu_ps float @test1(i32 inreg %idx0, i32 inreg %idx1) {
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main_body:
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%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
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%out = fadd float %src0, %src1
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%out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
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ret float %out.0
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}
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; Check that the softwqm intrinsic works correctly for integers.
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;
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;CHECK-LABEL: {{^}}test2:
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;CHECK-NOT: s_wqm_b64 exec, exec
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;CHECK: buffer_load_dword
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;CHECK: buffer_load_dword
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;CHECK: v_add_f32_e32
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define amdgpu_ps float @test2(i32 inreg %idx0, i32 inreg %idx1) {
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main_body:
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%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
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%out = fadd float %src0, %src1
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%out.0 = bitcast float %out to i32
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%out.1 = call i32 @llvm.amdgcn.softwqm.i32(i32 %out.0)
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%out.2 = bitcast i32 %out.1 to float
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ret float %out.2
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}
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; Make sure the transition from WQM to Exact to softwqm does not trigger WQM.
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;
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;CHECK-LABEL: {{^}}test_softwqm1:
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;CHECK-NOT: s_wqm_b64 exec, exec
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;CHECK: buffer_load_dword
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;CHECK: buffer_load_dword
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;CHECK: buffer_store_dword
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;CHECK-NOT; s_wqm_b64 exec, exec
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;CHECK: v_add_f32_e32
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define amdgpu_ps float @test_softwqm1(i32 inreg %idx0, i32 inreg %idx1) {
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main_body:
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%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
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%temp = fadd float %src0, %src1
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call void @llvm.amdgcn.struct.buffer.store.f32(float %temp, <4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%out = fadd float %temp, %temp
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%out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
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ret float %out.0
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}
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; Make sure the transition from WQM to Exact to softwqm does trigger WQM.
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;
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;CHECK-LABEL: {{^}}test_softwqm2:
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;CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK: s_wqm_b64 exec, exec
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;CHECK: buffer_load_dword
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;CHECK: buffer_load_dword
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;CHECK: v_add_f32_e32
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;CHECK: v_add_f32_e32
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;CHECK: buffer_store_dword
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define amdgpu_ps float @test_softwqm2(i32 inreg %idx0, i32 inreg %idx1) {
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main_body:
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%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
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%temp = fadd float %src0, %src1
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%temp.0 = call float @llvm.amdgcn.wqm.f32(float %temp)
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call void @llvm.amdgcn.struct.buffer.store.f32(float %temp.0, <4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%out = fadd float %temp, %temp
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%out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
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ret float %out.0
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}
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; Make sure the transition from Exact to WWM then softwqm does not trigger WQM.
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;
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;CHECK-LABEL: {{^}}test_wwm1:
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;CHECK: s_or_saveexec_b64 [[ORIG0:s\[[0-9]+:[0-9]+\]]], -1
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;CHECK: buffer_load_dword
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;CHECK: s_mov_b64 exec, [[ORIG0]]
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;CHECK: buffer_store_dword
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;CHECK: s_or_saveexec_b64 [[ORIG1:s\[[0-9]+:[0-9]+\]]], -1
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;CHECK: buffer_load_dword
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;CHECK: v_add_f32_e32
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;CHECK: s_mov_b64 exec, [[ORIG1]]
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;CHECK-NOT: s_wqm_b64
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define amdgpu_ps float @test_wwm1(i32 inreg %idx0, i32 inreg %idx1) {
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main_body:
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%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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call void @llvm.amdgcn.struct.buffer.store.f32(float %src0, <4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
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%temp = fadd float %src0, %src1
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%temp.0 = call float @llvm.amdgcn.wwm.f32(float %temp)
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%out = fadd float %temp.0, %temp.0
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%out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
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ret float %out.0
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}
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; Check that softwqm on one case of branch does not trigger WQM for shader.
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;
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;CHECK-LABEL: {{^}}test_control_flow_0:
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;CHECK-NEXT: ; %main_body
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;CHECK-NOT: s_wqm_b64 exec, exec
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;CHECK: %ELSE
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;CHECK: store
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;CHECK: %IF
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;CHECK: buffer_load
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;CHECK: buffer_load
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define amdgpu_ps float @test_control_flow_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 inreg %idx0, i32 inreg %idx1, i32 %c, i32 %z, float %data) {
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main_body:
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%cmp = icmp eq i32 %z, 0
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br i1 %cmp, label %IF, label %ELSE
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IF:
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%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
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%out = fadd float %src0, %src1
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%data.if = call float @llvm.amdgcn.softwqm.f32(float %out)
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br label %END
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ELSE:
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call void @llvm.amdgcn.struct.buffer.store.f32(float %data, <4 x i32> undef, i32 %c, i32 0, i32 0, i32 0)
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br label %END
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END:
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%r = phi float [ %data.if, %IF ], [ %data, %ELSE ]
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ret float %r
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}
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; Check that softwqm on one case of branch is treated as WQM in WQM shader.
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;
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;CHECK-LABEL: {{^}}test_control_flow_1:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: %ELSE
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;CHECK: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
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;CHECK: store
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;CHECK: s_mov_b64 exec, [[SAVED]]
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;CHECK: %IF
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;CHECK-NOT: s_and_saveexec_b64
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;CHECK-NOT: s_and_b64 exec
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;CHECK: buffer_load
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;CHECK: buffer_load
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define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 inreg %idx0, i32 inreg %idx1, i32 %c, i32 %z, float %data) {
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main_body:
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%c.bc = bitcast i32 %c to float
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%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.bc, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
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%tex0 = extractelement <4 x float> %tex, i32 0
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%dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
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%data.sample = extractelement <4 x float> %dtex, i32 0
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%cmp = icmp eq i32 %z, 0
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br i1 %cmp, label %IF, label %ELSE
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IF:
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%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
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%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
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%out = fadd float %src0, %src1
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%data.if = call float @llvm.amdgcn.softwqm.f32(float %out)
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br label %END
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ELSE:
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call void @llvm.amdgcn.struct.buffer.store.f32(float %data.sample, <4 x i32> undef, i32 %c, i32 0, i32 0, i32 0)
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br label %END
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END:
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%r = phi float [ %data.if, %IF ], [ %data, %ELSE ]
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ret float %r
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}
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declare void @llvm.amdgcn.struct.buffer.store.f32(float, <4 x i32>, i32, i32, i32, i32 immarg) #2
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declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg) #2
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declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg) #3
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3
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declare void @llvm.amdgcn.kill(i1) #1
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declare float @llvm.amdgcn.wqm.f32(float) #3
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declare float @llvm.amdgcn.softwqm.f32(float) #3
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declare i32 @llvm.amdgcn.softwqm.i32(i32) #3
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declare float @llvm.amdgcn.wwm.f32(float) #3
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readonly }
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attributes #3 = { nounwind readnone }
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