2291bd137d
Support for XNACK and SRAMECC is not static on some GPUs. We must be able to differentiate between different scenarios for these dynamic subtarget features. The possible settings are: - Unsupported: The GPU has no support for XNACK/SRAMECC. - Any: Preference is unspecified. Use conservative settings that can run anywhere. - Off: Request support for XNACK/SRAMECC Off - On: Request support for XNACK/SRAMECC On GCNSubtarget will track the four options based on the following criteria. If the subtarget does not support XNACK/SRAMECC we say the setting is "Unsupported". If no subtarget features for XNACK/SRAMECC are requested we must support "Any" mode. If the subtarget features XNACK/SRAMECC exist in the feature string when initializing the subtarget, the settings are "On/Off". The defaults are updated to be conservatively correct, meaning if no setting for XNACK or SRAMECC is explicitly requested, defaults will be used which generate code that can be run anywhere. This corresponds to the "Any" setting. Differential Revision: https://reviews.llvm.org/D85882
115 lines
5.9 KiB
LLVM
115 lines
5.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefixes=CHECK,GFX6 %s
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; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck --check-prefix=CHECK %s
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; RUN: llc -march=amdgcn -mattr=-xnack -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=CHECK,GFX9-FLATSCR,FLATSCR %s
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; RUN: llc -march=amdgcn -mcpu=gfx1030 -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=CHECK,GFX10-FLATSCR,FLATSCR %s
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;
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; There is something about Tonga that causes this test to spend a lot of time
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; in the default register allocator.
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; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
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; is used to calculate the scratch load/store address. Make sure that this
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; mechanism works even when many spills happen.
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; Just test that it compiles successfully.
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; CHECK-LABEL: test
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; GFX9-FLATSCR: s_mov_b32 [[SOFF1:s[0-9]+]], 4{{$}}
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; GFX9-FLATSCR: scratch_store_dwordx4 off, v[{{[0-9:]+}}], [[SOFF1]] ; 16-byte Folded Spill
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; GFX9-FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x{{[0-9a-f]+}}{{$}}
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; GFX9-FLATSCR: scratch_load_dwordx4 v[{{[0-9:]+}}], off, [[SOFF2]] ; 16-byte Folded Reload
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; GFX10-FLATSCR: scratch_store_dwordx4 off, v[{{[0-9:]+}}], off offset:{{[0-9]+}} ; 16-byte Folded Spill
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; GFX10-FLATSCR: scratch_load_dwordx4 v[{{[0-9:]+}}], off, off offset:{{[0-9]+}} ; 16-byte Folded Reload
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define amdgpu_kernel void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) {
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entry:
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid
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%a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr
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; mark most VGPR registers as used to increase register pressure
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call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" ()
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call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" ()
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call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" ()
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call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" ()
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call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" ()
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call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" ()
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call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" ()
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%outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid
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store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr
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ret void
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}
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; CHECK-LABEL: test_limited_sgpr
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; GFX6: s_add_u32 s32, s32, 0x[[OFFSET:[0-9a-f]+]]
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; GFX6-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9:]+}}], s32
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; GFX6-NEXT: s_sub_u32 s32, s32, 0x[[OFFSET:[0-9a-f]+]]
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; GFX6: NumSgprs: 48
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; GFX6: ScratchSize: 8608
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; FLATSCR: s_movk_i32 [[SOFF1:s[0-9]+]], 0x
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; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
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; FLATSCR-NEXT: scratch_store_dwordx4 off, v[{{[0-9:]+}}], [[SOFF1]] ; 16-byte Folded Spill
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; FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x
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; FLATSCR: scratch_load_dwordx4 v[{{[0-9:]+}}], off, [[SOFF2]] ; 16-byte Folded Reload
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define amdgpu_kernel void @test_limited_sgpr(<64 x i32> addrspace(1)* %out, <64 x i32> addrspace(1)* %in) #0 {
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entry:
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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; allocate enough scratch to go beyond 2^12 addressing
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%scratch = alloca <1280 x i32>, align 8, addrspace(5)
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; load VGPR data
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%aptr = getelementptr <64 x i32>, <64 x i32> addrspace(1)* %in, i32 %tid
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%a = load <64 x i32>, <64 x i32> addrspace(1)* %aptr
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; make sure scratch is used
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%x = extractelement <64 x i32> %a, i32 0
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%sptr0 = getelementptr <1280 x i32>, <1280 x i32> addrspace(5)* %scratch, i32 %x, i32 0
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store i32 1, i32 addrspace(5)* %sptr0
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; fill up SGPRs
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%sgpr0 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr1 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr2 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr4 = call <4 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr5 = call <2 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr6 = call <2 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr7 = call i32 asm sideeffect "; def $0", "=s" ()
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%cmp = icmp eq i32 %x, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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; create SGPR pressure
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call void asm sideeffect "; use $0,$1,$2,$3,$4,$5,$6", "s,s,s,s,s,s,s,s"(<8 x i32> %sgpr0, <8 x i32> %sgpr1, <8 x i32> %sgpr2, <8 x i32> %sgpr3, <4 x i32> %sgpr4, <2 x i32> %sgpr5, <2 x i32> %sgpr6, i32 %sgpr7)
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; mark most VGPR registers as used to increase register pressure
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call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" ()
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call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" ()
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call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" ()
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call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" ()
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call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" ()
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call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" ()
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call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" ()
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br label %ret
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ret:
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%outptr = getelementptr <64 x i32>, <64 x i32> addrspace(1)* %out, i32 %tid
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store <64 x i32> %a, <64 x i32> addrspace(1)* %outptr
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
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attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
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attributes #1 = { nounwind readnone }
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