2291bd137d
Support for XNACK and SRAMECC is not static on some GPUs. We must be able to differentiate between different scenarios for these dynamic subtarget features. The possible settings are: - Unsupported: The GPU has no support for XNACK/SRAMECC. - Any: Preference is unspecified. Use conservative settings that can run anywhere. - Off: Request support for XNACK/SRAMECC Off - On: Request support for XNACK/SRAMECC On GCNSubtarget will track the four options based on the following criteria. If the subtarget does not support XNACK/SRAMECC we say the setting is "Unsupported". If no subtarget features for XNACK/SRAMECC are requested we must support "Any" mode. If the subtarget features XNACK/SRAMECC exist in the feature string when initializing the subtarget, the settings are "On/Off". The defaults are updated to be conservatively correct, meaning if no setting for XNACK or SRAMECC is explicitly requested, defaults will be used which generate code that can be run anywhere. This corresponds to the "Any" setting. Differential Revision: https://reviews.llvm.org/D85882
49 lines
1.9 KiB
LLVM
49 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GCN
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define void @vgpr_descriptor_waterfall_loop_idom_update(<4 x i32>* %arg) #0 {
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; GCN-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_waitcnt_vscnt null, 0x0
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; GCN-NEXT: BB0_1: ; %bb0
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; GCN-NEXT: ; =>This Loop Header: Depth=1
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; GCN-NEXT: ; Child Loop BB0_2 Depth 2
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; GCN-NEXT: v_add_co_u32_e64 v6, vcc_lo, v0, 8
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; GCN-NEXT: s_mov_b32 s5, exec_lo
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; GCN-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: flat_load_dwordx2 v[4:5], v[6:7]
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; GCN-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
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; GCN-NEXT: BB0_2: ; Parent Loop BB0_1 Depth=1
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; GCN-NEXT: ; => This Inner Loop Header: Depth=2
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s8, v2
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; GCN-NEXT: v_readfirstlane_b32 s9, v3
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; GCN-NEXT: v_readfirstlane_b32 s10, v4
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; GCN-NEXT: v_readfirstlane_b32 s11, v5
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; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[2:3]
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; GCN-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[4:5]
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; GCN-NEXT: s_and_b32 s4, vcc_lo, s4
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; GCN-NEXT: s_and_saveexec_b32 s4, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_store_dword v0, v0, s[8:11], 0 offen
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; GCN-NEXT: s_waitcnt_depctr 0xffe3
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; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_cbranch_execnz BB0_2
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; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_1 Depth=1
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; GCN-NEXT: s_mov_b32 exec_lo, s5
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; GCN-NEXT: s_branch BB0_1
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entry:
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br label %bb0
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bb0:
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%desc = load <4 x i32>, <4 x i32>* %arg, align 8
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tail call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> %desc, i32 undef, i32 0, i32 0)
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br label %bb0
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}
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declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
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attributes #0 = { nounwind writeonly }
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