7efabe5c7d
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
140 lines
4.2 KiB
YAML
140 lines
4.2 KiB
YAML
# RUN: llc -O0 -mtriple arm-- -mattr=+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
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# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
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# RUN: llc -O0 -mtriple arm-- -mattr=+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
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# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
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--- |
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define void @test_fpconst_zero_s32() { ret void }
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define void @test_fpconst_zero_s64() { ret void }
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define void @test_fpconst_8bit_s32() { ret void }
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define void @test_fpconst_8bit_s64() { ret void }
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...
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---
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name: test_fpconst_zero_s32
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# CHECK-LABEL: name: test_fpconst_zero_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: fprb }
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# CHECK: constants:
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# CHECK-NEXT: id: 0
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# CHECK-NEXT: value: 'float 0.000000e+00'
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# CHECK-NEXT: alignment: 4
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# CHECK-NEXT: isTargetSpecific: false
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = G_FCONSTANT float 0.0
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; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
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G_STORE %1(s32), %0 :: (store 4)
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; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
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BX_RET 14, $noreg
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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...
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---
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name: test_fpconst_zero_s64
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# CHECK-LABEL: name: test_fpconst_zero_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: fprb }
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# CHECK: constants:
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# CHECK-NEXT: id: 0
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# CHECK-NEXT: value: 'double 0.000000e+00'
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# CHECK-NEXT: alignment: 8
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# CHECK-NEXT: isTargetSpecific: false
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s64) = G_FCONSTANT double 0.0
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; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constant-pool)
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G_STORE %1(s64), %0 :: (store 8)
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; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
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BX_RET 14, $noreg
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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...
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---
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name: test_fpconst_8bit_s32
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# CHECK-LABEL: name: test_fpconst_8bit_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: fprb }
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# VFP3: constants: []
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# VFP2: constants:
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# VFP2-NEXT: id: 0
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# VFP2-NEXT: value: 'float -2.000000e+00'
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# VFP2-NEXT: alignment: 4
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# VFP2-NEXT: isTargetSpecific: false
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = G_FCONSTANT float -2.0
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; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 /* CC::al */, $noreg
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; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
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G_STORE %1(s32), %0 :: (store 4)
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; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
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BX_RET 14, $noreg
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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...
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---
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name: test_fpconst_8bit_s64
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# CHECK-LABEL: name: test_fpconst_8bit_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: fprb }
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# VFP3: constants: []
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# VFP2: constants:
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# VFP2-NEXT: id: 0
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# VFP2-NEXT: value: double 5.000000e-01
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# VFP2-NEXT: alignment: 8
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# VFP2-NEXT: isTargetSpecific: false
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s64) = G_FCONSTANT double 5.0e-1
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; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14 /* CC::al */, $noreg
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; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constant-pool)
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G_STORE %1(s64), %0 :: (store 8)
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; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
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BX_RET 14, $noreg
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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...
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