7fff1fbd3c
This hashing scheme has been useful out of tree, and I want to start experimenting with it. Specifically I want to experiment on the MIRVRegNamer, MIRCanononicalizer, and eventually the MachineOutliner. This diff is a first step, that optionally brings stable hashing to the MIRVRegNamer (and as a result, the MIRCanonicalizer). We've tested this hashing scheme on a lot of MachineOperand types that llvm::hash_value can not handle in a stable manner. This stable hashing was also the basis for "Global Machine Outliner for ThinLTO" in EuroLLVM 2020 http://llvm.org/devmtg/2020-04/talks.html#TechTalk_58 Credits: Kyungwoo Lee, Nikolai Tillmann Differential Revision: https://reviews.llvm.org/D86952
44 lines
2.1 KiB
YAML
44 lines
2.1 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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define amdgpu_kernel void @f(i32 addrspace(1)* nocapture %arg) {
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unreachable
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}
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...
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---
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name: f
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alignment: 1
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_64_xexec }
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- { id: 2, class: sreg_64_xexec }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_64_xexec }
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liveins:
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- { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }
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body: |
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bb.0:
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liveins: $sgpr4_sgpr5
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; CHECK: COPY
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
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%0 = COPY $sgpr4_sgpr5
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%1 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
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%2 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
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%3 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( invariant load 8 from `i64 addrspace(4)* undef`)
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%4 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( load 8 from `i64 addrspace(4)* undef`)
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%5 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( load 8 from `i64 addrspace(2)* undef`)
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%6 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( load 8 from `i64 addrspace(1)* undef`)
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...
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