be7d425edc
This patch is the initial patch for support of the AIX extended vector ABI. The extended ABI treats vector registers V20-V31 as non-volatile and we add them as callee saved registers in this patch. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D88676
76 lines
3.1 KiB
LLVM
76 lines
3.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
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; RUN: --check-prefix=32SMALL-MIR %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
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; RUN: --check-prefix=32LARGE-MIR %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
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; RUN: --check-prefix=64SMALL-MIR %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
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; RUN: --check-prefix=64LARGE-MIR %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s
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define void @foo() {
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entry:
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%tmp = alloca i64
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br label %__here
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__here:
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store i64 ptrtoint (i8* blockaddress(@foo, %__here) to i64), i64* %tmp
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ret void
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}
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; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc blockaddress(@foo, %ir-block.__here), $r2 :: (load 4 from got)
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; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, blockaddress(@foo, %ir-block.__here)
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; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL blockaddress(@foo, %ir-block.__here), killed renamable $r[[REG1]], implicit $r2 :: (load 4 from got)
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; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocBA blockaddress(@foo, %ir-block.__here), $x2 :: (load 8 from got)
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; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, blockaddress(@foo, %ir-block.__here)
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; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL blockaddress(@foo, %ir-block.__here), killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
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; 32SMALL-ASM-LABEL: foo
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; 32SMALL-ASM: .foo:
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; 32SMALL-ASM: L..tmp0:
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; 32SMALL-ASM: lwz [[REG1:[0-9]+]], L..C0(2)
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; 32LARGE-ASM-LABEL: foo
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; 32LARGE-ASM: .foo:
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; 32LARGE-ASM: L..tmp0:
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; 32LARGE-ASM: addis [[REG1:[0-9]+]], L..C0@u(2)
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; 32LARGE-ASM: lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
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; 64SMALL-ASM-LABEL: foo
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; 64SMALL-ASM: .foo:
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; 64SMALL-ASM: L..tmp0:
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; 64SMALL-ASM: ld [[REG1:[0-9]+]], L..C0(2)
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; 64LARGE-ASM-LABEL: foo
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; 64LARGE-ASM: .foo:
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; 64LARGE-ASM: L..tmp0:
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; 64LARGE-ASM: addis [[REG1:[0-9]+]], L..C0@u(2)
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; 64LARGE-ASM: ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
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; SMALL-ASM: .toc
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; SMALL-ASM: .tc L..tmp0[TC],L..tmp0
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; LARGE-ASM: .toc
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; LARGE-ASM: .tc L..tmp0[TE],L..tmp0
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