llvm-project/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
Zarko Todorovski be7d425edc [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI
This patch is the initial patch for support of the AIX extended vector ABI.  The extended ABI treats vector registers V20-V31 as non-volatile and we add them as callee saved registers in this patch.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D88676
2020-11-24 23:01:51 -05:00

77 lines
3.2 KiB
YAML

# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
# RUN: FileCheck %s --check-prefixes=CHECK
---
name: CRMultiSave
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$r3', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r3
renamable $r29 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
renamable $cr2lt = COPY $cr0gt
renamable $cr4lt = COPY $cr0gt
renamable $r3 = COPY $r29
BLR implicit $lr, implicit $rm, implicit $r3
; CHECK-LABEL: fixedStack:
; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default,
; CHECK-NEXT: callee-saved-register: '$r29', callee-saved-restored: true, debug-info-variable: '',
; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
; CHECK-NEXT: - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
; CHECK-NEXT: debug-info-location: '' }
; CHECK-LABEL: stack:
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $r3, $r29, $cr2, $cr4
; CHECK: $r12 = MFCR implicit killed $cr2, implicit killed $cr4
; CHECK-NEXT: STW killed $r12, 4, $r1
; CHECK-NEXT: STW killed $r29, -12, $r1 :: (store 4 into %fixed-stack.0)
; CHECK: $r29 = LWZ -12, $r1 :: (load 4 from %fixed-stack.0)
; CHECK-NEXT: $r12 = LWZ 4, $r1
; CHECK-NEXT: $cr2 = MTOCRF $r12
; CHECK-NEXT: $cr4 = MTOCRF killed $r12
...
---
name: CR3Save
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$r3', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r3
renamable $r14 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
renamable $cr3lt = COPY $cr0gt
renamable $r3 = COPY $r14
BLR implicit $lr, implicit $rm, implicit $r3
; CHECK-LABEL: fixedStack:
; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -72, size: 4, alignment: 8, stack-id: default,
; CHECK-NEXT: callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
; CHECK-NEXT: - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr3',
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
; CHECK-NEXT: debug-info-location: '' }
; CHECK-LABEL: stack:
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $r3, $r14, $cr3
; CHECK: $r12 = MFCR implicit killed $cr3
; CHECK-NEXT: STW killed $r12, 4, $r1
; CHECK-NEXT: STW killed $r14, -72, $r1 :: (store 4 into %fixed-stack.0, align 8)
; CHECK: $r14 = LWZ -72, $r1 :: (load 4 from %fixed-stack.0, align 8)
; CHECK-NEXT: $r12 = LWZ 4, $r1
; CHECK-NEXT: $cr3 = MTOCRF killed $r12