4e127bce2d
Do not defer to the base class when the register constraint is a physical fpr. The base class will select SPILLTOVSRRC as the register class and register allocation will fail on subtargets without VSX registers. Differential Revision: https://reviews.llvm.org/D91629
27 lines
774 B
LLVM
27 lines
774 B
LLVM
; RUN: llc -mcpu=pwr7 -mattr=-altivec -verify-machineinstrs \
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; RUN: -mtriple=powerpc-unknown-aix < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -mattr=-altivec -verify-machineinstrs \
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; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s
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define dso_local double @test_double(double %a, double %b) {
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entry:
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%0 = tail call double asm "fadd. $0,$1,$2\0A", "={f31},d,d,0"(double %a, double %b, double 0.000000e+00)
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ret double %0
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}
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; CHECK-LABEL: test_double
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; CHECK: #APP
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; CHECK-NEXT: fadd. 31,1,2
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define dso_local signext i32 @test_int(double %a, double %b) {
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entry:
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%0 = tail call i32 asm "fadd. $0,$1,$2\0A", "={f0},d,d,0"(double %a, double %b, i32 0)
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ret i32 %0
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}
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; CHECK-LABEL: test_int
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; CHECK: #APP
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; CHECK-NEXT: fadd. 0,1,2
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