0d47c7aba3
Summary: Introduces the `InstrInfo::areMemAccessesTriviallyDisjoint` hook. The test could check for instruction reorderings, but to avoid being brittle it just checks instruction dependencies. Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D67046
27 lines
1.1 KiB
LLVM
27 lines
1.1 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc -mtriple=riscv32 -debug-only=machine-scheduler < %s \
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; RUN: -o /dev/null 2>&1 | FileCheck %s
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; RUN: llc -mtriple=riscv64 -debug-only=machine-scheduler < %s \
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; RUN: -o /dev/null 2>&1 | FileCheck %s
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; This test exercises the areMemAccessesTriviallyDisjoint hook.
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; Test that the two stores are disjoint memory accesses. If the corresponding
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; store machine instructions don't depend on each other, the second store should
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; not appear in the successors list of the first one and the first one should
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; not appear on the predecessors list of the second one.
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define i32 @test_disjoint(i32* %P, i32 %v) {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: test_disjoint:%bb.0
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; CHECK:SU(2): SW %1:gpr, %0:gpr, 12 :: (store 4 into %ir.arrayidx)
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; CHECK-NOT: Successors:
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; CHECK:SU(3): SW %1:gpr, %0:gpr, 8 :: (store 4 into %ir.arrayidx1)
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; CHECK: Predecessors:
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; CHECK-NOT: SU(2): Ord Latency=0 Memory
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%arrayidx = getelementptr inbounds i32, i32* %P, i32 3
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store i32 %v, i32* %arrayidx
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%arrayidx1 = getelementptr inbounds i32, i32* %P, i32 2
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store i32 %v, i32* %arrayidx1
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ret i32 %v
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}
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