5a31a67385
This patch proposes how to deal with RISC-V vector frame objects. The layout of RISC-V vector frame will look like |---------------------------------| | scalar callee-saved registers | |---------------------------------| | scalar local variables | |---------------------------------| | scalar outgoing arguments | |---------------------------------| | RVV local variables && | | RVV outgoing arguments | |---------------------------------| <- end of frame (sp) If there is realignment or variable length array in the stack, we will use frame pointer to access fixed objects and stack pointer to access non-fixed objects. |---------------------------------| <- frame pointer (fp) | scalar callee-saved registers | |---------------------------------| | scalar local variables | |---------------------------------| | ///// realignment ///// | |---------------------------------| | scalar outgoing arguments | |---------------------------------| | RVV local variables && | | RVV outgoing arguments | |---------------------------------| <- end of frame (sp) If there are both realignment and variable length array in the stack, we will use frame pointer to access fixed objects and base pointer to access non-fixed objects. |---------------------------------| <- frame pointer (fp) | scalar callee-saved registers | |---------------------------------| | scalar local variables | |---------------------------------| | ///// realignment ///// | |---------------------------------| <- base pointer (bp) | RVV local variables && | | RVV outgoing arguments | |---------------------------------| | /////////////////////////////// | | variable length array | | /////////////////////////////// | |---------------------------------| <- end of frame (sp) | scalar outgoing arguments | |---------------------------------| In this version, we do not save the addresses of RVV objects in the stack. We access them directly through the polynomial expression (a x VLENB + b). We do not reserve frame pointer when there is any RVV object in the stack. So, we also access the scalar frame objects through the polynomial expression (a x VLENB + b) if the access across RVV stack area. Differential Revision: https://reviews.llvm.org/D94465
281 lines
9.5 KiB
LLVM
281 lines
9.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IV
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define void @local_var_mf8() {
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; RV64IV-LABEL: local_var_mf8:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: .cfi_def_cfa_offset 0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vle8.v v25, (a0)
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; RV64IV-NEXT: vle8.v v25, (sp)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: add sp, sp, a0
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; RV64IV-NEXT: ret
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%local0 = alloca <vscale x 1 x i8>
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%local1 = alloca <vscale x 1 x i8>
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load volatile <vscale x 1 x i8>, <vscale x 1 x i8>* %local0
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load volatile <vscale x 1 x i8>, <vscale x 1 x i8>* %local1
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ret void
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}
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define void @local_var_m1() {
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; RV64IV-LABEL: local_var_m1:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: .cfi_def_cfa_offset 0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl1r.v v25, (a0)
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; RV64IV-NEXT: vl1r.v v25, (sp)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: add sp, sp, a0
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; RV64IV-NEXT: ret
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%local0 = alloca <vscale x 8 x i8>
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%local1 = alloca <vscale x 8 x i8>
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load volatile <vscale x 8 x i8>, <vscale x 8 x i8>* %local0
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load volatile <vscale x 8 x i8>, <vscale x 8 x i8>* %local1
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ret void
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}
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define void @local_var_m2() {
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; RV64IV-LABEL: local_var_m2:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: .cfi_def_cfa_offset 0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl2r.v v26, (a0)
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; RV64IV-NEXT: vl2r.v v26, (sp)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: add sp, sp, a0
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; RV64IV-NEXT: ret
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%local0 = alloca <vscale x 16 x i8>
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%local1 = alloca <vscale x 16 x i8>
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1
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ret void
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}
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define void @local_var_m4() {
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; RV64IV-LABEL: local_var_m4:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -32
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; RV64IV-NEXT: .cfi_def_cfa_offset 32
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; RV64IV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: .cfi_offset ra, -8
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; RV64IV-NEXT: .cfi_offset s0, -16
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; RV64IV-NEXT: addi s0, sp, 32
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; RV64IV-NEXT: .cfi_def_cfa s0, 0
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; RV64IV-NEXT: andi sp, sp, -32
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 3
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl4r.v v28, (a0)
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; RV64IV-NEXT: vl4r.v v28, (sp)
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; RV64IV-NEXT: addi sp, s0, -32
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; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: addi sp, sp, 32
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; RV64IV-NEXT: ret
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%local0 = alloca <vscale x 32 x i8>
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%local1 = alloca <vscale x 32 x i8>
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load volatile <vscale x 32 x i8>, <vscale x 32 x i8>* %local0
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load volatile <vscale x 32 x i8>, <vscale x 32 x i8>* %local1
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ret void
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}
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define void @local_var_m8() {
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; RV64IV-LABEL: local_var_m8:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -64
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; RV64IV-NEXT: .cfi_def_cfa_offset 64
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; RV64IV-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: .cfi_offset ra, -8
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; RV64IV-NEXT: .cfi_offset s0, -16
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; RV64IV-NEXT: addi s0, sp, 64
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; RV64IV-NEXT: .cfi_def_cfa s0, 0
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; RV64IV-NEXT: andi sp, sp, -64
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 4
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 3
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl8r.v v8, (a0)
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; RV64IV-NEXT: vl8r.v v8, (sp)
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; RV64IV-NEXT: addi sp, s0, -64
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; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: addi sp, sp, 64
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; RV64IV-NEXT: ret
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%local0 = alloca <vscale x 64 x i8>
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%local1 = alloca <vscale x 64 x i8>
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load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0
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load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1
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ret void
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}
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define void @local_var_m2_mix_local_scalar() {
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; RV64IV-LABEL: local_var_m2_mix_local_scalar:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -16
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; RV64IV-NEXT: .cfi_def_cfa_offset 16
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: lw a0, 12(a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl2r.v v26, (a0)
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; RV64IV-NEXT: vl2r.v v26, (sp)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: lw a0, 8(a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: add sp, sp, a0
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; RV64IV-NEXT: addi sp, sp, 16
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; RV64IV-NEXT: ret
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%local_scalar0 = alloca i32
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%local0 = alloca <vscale x 16 x i8>
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%local1 = alloca <vscale x 16 x i8>
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%local_scalar1 = alloca i32
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load volatile i32, i32* %local_scalar0
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1
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load volatile i32, i32* %local_scalar1
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ret void
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}
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define void @local_var_m2_with_varsize_object(i64 %n) {
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; RV64IV-LABEL: local_var_m2_with_varsize_object:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -16
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; RV64IV-NEXT: .cfi_def_cfa_offset 16
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; RV64IV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: .cfi_offset ra, -8
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; RV64IV-NEXT: .cfi_offset s0, -16
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; RV64IV-NEXT: addi s0, sp, 16
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; RV64IV-NEXT: .cfi_def_cfa s0, 0
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; RV64IV-NEXT: csrr a1, vlenb
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; RV64IV-NEXT: slli a1, a1, 2
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; RV64IV-NEXT: sub sp, sp, a1
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; RV64IV-NEXT: addi a0, a0, 15
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; RV64IV-NEXT: andi a0, a0, -16
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; RV64IV-NEXT: sub a0, sp, a0
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; RV64IV-NEXT: mv sp, a0
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; RV64IV-NEXT: csrr a1, vlenb
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; RV64IV-NEXT: slli a1, a1, 1
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; RV64IV-NEXT: sub a1, s0, a1
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; RV64IV-NEXT: addi a1, a1, -16
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; RV64IV-NEXT: call notdead@plt
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: sub a0, s0, a0
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; RV64IV-NEXT: addi a0, a0, -16
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; RV64IV-NEXT: vl2r.v v26, (a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: sub a0, s0, a0
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; RV64IV-NEXT: addi a0, a0, -16
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; RV64IV-NEXT: vl2r.v v26, (a0)
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; RV64IV-NEXT: addi sp, s0, -16
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; RV64IV-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: addi sp, sp, 16
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; RV64IV-NEXT: ret
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%1 = alloca i8, i64 %n
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%2 = alloca <vscale x 16 x i8>
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%3 = alloca <vscale x 16 x i8>
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call void @notdead(i8* %1, <vscale x 16 x i8>* %2)
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %2
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %3
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ret void
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}
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define void @local_var_m2_with_bp(i64 %n) {
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; RV64IV-LABEL: local_var_m2_with_bp:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -256
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; RV64IV-NEXT: .cfi_def_cfa_offset 256
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; RV64IV-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: sd s1, 232(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: .cfi_offset ra, -8
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; RV64IV-NEXT: .cfi_offset s0, -16
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; RV64IV-NEXT: .cfi_offset s1, -24
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; RV64IV-NEXT: addi s0, sp, 256
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; RV64IV-NEXT: .cfi_def_cfa s0, 0
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; RV64IV-NEXT: andi sp, sp, -128
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; RV64IV-NEXT: mv s1, sp
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; RV64IV-NEXT: csrr a1, vlenb
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; RV64IV-NEXT: slli a1, a1, 2
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; RV64IV-NEXT: sub sp, sp, a1
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; RV64IV-NEXT: addi a0, a0, 15
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; RV64IV-NEXT: andi a0, a0, -16
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; RV64IV-NEXT: sub a0, sp, a0
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; RV64IV-NEXT: mv sp, a0
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; RV64IV-NEXT: addi a1, s1, 128
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; RV64IV-NEXT: csrr a2, vlenb
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; RV64IV-NEXT: slli a2, a2, 1
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; RV64IV-NEXT: sub a2, s1, a2
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; RV64IV-NEXT: mv a2, a2
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; RV64IV-NEXT: call notdead2@plt
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; RV64IV-NEXT: lw a0, 124(s1)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: sub a0, s1, a0
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; RV64IV-NEXT: vl2r.v v26, (a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 2
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; RV64IV-NEXT: sub a0, s1, a0
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; RV64IV-NEXT: vl2r.v v26, (a0)
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; RV64IV-NEXT: lw a0, 120(s1)
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; RV64IV-NEXT: addi sp, s0, -256
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; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: addi sp, sp, 256
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; RV64IV-NEXT: ret
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%1 = alloca i8, i64 %n
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%2 = alloca i32, align 128
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%local_scalar0 = alloca i32
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%local0 = alloca <vscale x 16 x i8>
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%local1 = alloca <vscale x 16 x i8>
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%local_scalar1 = alloca i32
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call void @notdead2(i8* %1, i32* %2, <vscale x 16 x i8>* %local0)
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load volatile i32, i32* %local_scalar0
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1
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load volatile i32, i32* %local_scalar1
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ret void
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}
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declare void @notdead(i8*, <vscale x 16 x i8>*)
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declare void @notdead2(i8*, i32*, <vscale x 16 x i8>*)
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