5a31a67385
This patch proposes how to deal with RISC-V vector frame objects. The layout of RISC-V vector frame will look like |---------------------------------| | scalar callee-saved registers | |---------------------------------| | scalar local variables | |---------------------------------| | scalar outgoing arguments | |---------------------------------| | RVV local variables && | | RVV outgoing arguments | |---------------------------------| <- end of frame (sp) If there is realignment or variable length array in the stack, we will use frame pointer to access fixed objects and stack pointer to access non-fixed objects. |---------------------------------| <- frame pointer (fp) | scalar callee-saved registers | |---------------------------------| | scalar local variables | |---------------------------------| | ///// realignment ///// | |---------------------------------| | scalar outgoing arguments | |---------------------------------| | RVV local variables && | | RVV outgoing arguments | |---------------------------------| <- end of frame (sp) If there are both realignment and variable length array in the stack, we will use frame pointer to access fixed objects and base pointer to access non-fixed objects. |---------------------------------| <- frame pointer (fp) | scalar callee-saved registers | |---------------------------------| | scalar local variables | |---------------------------------| | ///// realignment ///// | |---------------------------------| <- base pointer (bp) | RVV local variables && | | RVV outgoing arguments | |---------------------------------| | /////////////////////////////// | | variable length array | | /////////////////////////////// | |---------------------------------| <- end of frame (sp) | scalar outgoing arguments | |---------------------------------| In this version, we do not save the addresses of RVV objects in the stack. We access them directly through the polynomial expression (a x VLENB + b). We do not reserve frame pointer when there is any RVV object in the stack. So, we also access the scalar frame objects through the polynomial expression (a x VLENB + b) if the access across RVV stack area. Differential Revision: https://reviews.llvm.org/D94465
73 lines
2.7 KiB
LLVM
73 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IV
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declare <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
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<vscale x 64 x i8>,
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<vscale x 64 x i8>,
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<vscale x 64 x i8>,
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i64);
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define <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2) {
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; RV64IV-LABEL: callee:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: vl8r.v v24, (a0)
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; RV64IV-NEXT: addi a0, zero, 1024
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; RV64IV-NEXT: vsetvli a0, a0, e8,m8,tu,mu
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; RV64IV-NEXT: vmacc.vv v8, v16, v24
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; RV64IV-NEXT: ret
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%ret = call <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
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<vscale x 64 x i8> %arg0,
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<vscale x 64 x i8> %arg1,
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<vscale x 64 x i8> %arg2, i64 1024)
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ret <vscale x 64 x i8> %ret
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}
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define <vscale x 64 x i8> @caller() {
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; RV64IV-LABEL: caller:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -64
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; RV64IV-NEXT: .cfi_def_cfa_offset 64
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; RV64IV-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: .cfi_offset ra, -8
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; RV64IV-NEXT: .cfi_offset s0, -16
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; RV64IV-NEXT: addi s0, sp, 64
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; RV64IV-NEXT: .cfi_def_cfa s0, 0
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; RV64IV-NEXT: andi sp, sp, -64
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 5
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: addi a1, zero, 24
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; RV64IV-NEXT: mul a0, a0, a1
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl8r.v v8, (a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 4
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl8r.v v16, (a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 3
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: vl8r.v v24, (a0)
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; RV64IV-NEXT: mv a0, sp
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; RV64IV-NEXT: vs8r.v v24, (sp)
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; RV64IV-NEXT: call callee@plt
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; RV64IV-NEXT: addi sp, s0, -64
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; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: addi sp, sp, 64
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; RV64IV-NEXT: ret
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%local0 = alloca <vscale x 64 x i8>
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%local1 = alloca <vscale x 64 x i8>
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%local2 = alloca <vscale x 64 x i8>
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%arg0 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0
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%arg1 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1
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%arg2 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local2
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%ret = call <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0,
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<vscale x 64 x i8> %arg1,
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<vscale x 64 x i8> %arg2)
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ret <vscale x 64 x i8> %ret
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}
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