024af42c60
The ISel patterns we have for truncating to i1's under MVE do not seem to be correct. Instead custom lower to icmp(ne, and(x, 1), 0). Differential Revision: https://reviews.llvm.org/D94226
337 lines
10 KiB
LLVM
337 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4i32(<4 x i32> %src) {
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; CHECK-LABEL: sext_v4i1_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.i8 q2, #0xff
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; CHECK-NEXT: vcmp.s32 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <4 x i32> %src, zeroinitializer
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%0 = sext <4 x i1> %c to <4 x i32>
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @sext_v8i1_v8i16(<8 x i16> %src) {
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; CHECK-LABEL: sext_v8i1_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x0
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; CHECK-NEXT: vmov.i8 q2, #0xff
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; CHECK-NEXT: vcmp.s16 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <8 x i16> %src, zeroinitializer
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%0 = sext <8 x i1> %c to <8 x i16>
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @sext_v16i1_v16i8(<16 x i8> %src) {
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; CHECK-LABEL: sext_v16i1_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q1, #0x0
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; CHECK-NEXT: vmov.i8 q2, #0xff
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; CHECK-NEXT: vcmp.s8 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <16 x i8> %src, zeroinitializer
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%0 = sext <16 x i1> %c to <16 x i8>
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i64> %src) {
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; CHECK-LABEL: sext_v2i1_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r1, s2
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: vmov r3, s0
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: vmov r1, s1
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; CHECK-NEXT: sbcs.w r0, r2, r0
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; CHECK-NEXT: mov.w r0, #0
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: rsbs r3, r3, #0
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; CHECK-NEXT: sbcs.w r1, r2, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <2 x i64> %src, zeroinitializer
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%0 = sext <2 x i1> %c to <2 x i64>
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_v4i1_v4i32(<4 x i32> %src) {
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; CHECK-LABEL: zext_v4i1_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.i32 q2, #0x1
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; CHECK-NEXT: vcmp.s32 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <4 x i32> %src, zeroinitializer
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%0 = zext <4 x i1> %c to <4 x i32>
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8i16(<8 x i16> %src) {
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; CHECK-LABEL: zext_v8i1_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0x1
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; CHECK-NEXT: vcmp.s16 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <8 x i16> %src, zeroinitializer
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%0 = zext <8 x i1> %c to <8 x i16>
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @zext_v16i1_v16i8(<16 x i8> %src) {
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; CHECK-LABEL: zext_v16i1_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q1, #0x0
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; CHECK-NEXT: vmov.i8 q2, #0x1
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; CHECK-NEXT: vcmp.s8 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <16 x i8> %src, zeroinitializer
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%0 = zext <16 x i1> %c to <16 x i8>
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2i64(<2 x i64> %src) {
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; CHECK-LABEL: zext_v2i1_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r2, s2
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; CHECK-NEXT: adr r1, .LCPI7_0
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: vmov r3, s0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: rsbs r2, r2, #0
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; CHECK-NEXT: vmov r2, s1
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; CHECK-NEXT: sbcs.w r1, r0, r1
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; CHECK-NEXT: mov.w r1, #0
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r1, #1
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: rsbs r3, r3, #0
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; CHECK-NEXT: sbcs.w r2, r0, r2
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: vmov q0[2], q0[0], r0, r1
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI7_0:
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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entry:
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%c = icmp sgt <2 x i64> %src, zeroinitializer
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%0 = zext <2 x i1> %c to <2 x i64>
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @trunc_v4i1_v4i32(<4 x i32> %src) {
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; CHECK-LABEL: trunc_v4i1_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q2, #0x1
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vand q2, q0, q2
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; CHECK-NEXT: vcmp.i32 ne, q2, zr
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <4 x i32> %src to <4 x i1>
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%1 = select <4 x i1> %0, <4 x i32> %src, <4 x i32> zeroinitializer
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ret <4 x i32> %1
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}
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define arm_aapcs_vfpcc <8 x i16> @trunc_v8i1_v8i16(<8 x i16> %src) {
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; CHECK-LABEL: trunc_v8i1_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q2, #0x1
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vand q2, q0, q2
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; CHECK-NEXT: vcmp.i16 ne, q2, zr
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <8 x i16> %src to <8 x i1>
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%1 = select <8 x i1> %0, <8 x i16> %src, <8 x i16> zeroinitializer
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ret <8 x i16> %1
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}
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define arm_aapcs_vfpcc <16 x i8> @trunc_v16i1_v16i8(<16 x i8> %src) {
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; CHECK-LABEL: trunc_v16i1_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q2, #0x1
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vand q2, q0, q2
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; CHECK-NEXT: vcmp.i8 ne, q2, zr
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <16 x i8> %src to <16 x i1>
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%1 = select <16 x i1> %0, <16 x i8> %src, <16 x i8> zeroinitializer
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ret <16 x i8> %1
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}
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define arm_aapcs_vfpcc <2 x i64> @trunc_v2i1_v2i64(<2 x i64> %src) {
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; CHECK-LABEL: trunc_v2i1_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: and r0, r0, #1
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; CHECK-NEXT: and r1, r1, #1
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; CHECK-NEXT: rsbs r0, r0, #0
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
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; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <2 x i64> %src to <2 x i1>
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%1 = select <2 x i1> %0, <2 x i64> %src, <2 x i64> zeroinitializer
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ret <2 x i64> %1
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}
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define arm_aapcs_vfpcc <4 x float> @uitofp_v4i1_v4f32(<4 x i32> %src) {
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; CHECK-LABEL: uitofp_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vcmp.s32 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <4 x i32> %src, zeroinitializer
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%0 = uitofp <4 x i1> %c to <4 x float>
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <4 x float> @sitofp_v4i1_v4f32(<4 x i32> %src) {
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; CHECK-LABEL: sitofp_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.f32 q2, #-1.000000e+00
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; CHECK-NEXT: vcmp.s32 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <4 x i32> %src, zeroinitializer
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%0 = sitofp <4 x i1> %c to <4 x float>
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <4 x float> @fptoui_v4i1_v4f32(<4 x float> %src) {
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; CHECK-LABEL: fptoui_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vcmp.f32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = fptoui <4 x float> %src to <4 x i1>
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%s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer
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ret <4 x float> %s
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}
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define arm_aapcs_vfpcc <4 x float> @fptosi_v4i1_v4f32(<4 x float> %src) {
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; CHECK-LABEL: fptosi_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vcmp.f32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = fptosi <4 x float> %src to <4 x i1>
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%s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer
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ret <4 x float> %s
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}
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define arm_aapcs_vfpcc <8 x half> @uitofp_v8i1_v8f16(<8 x i16> %src) {
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; CHECK-LABEL: uitofp_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0x3c00
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; CHECK-NEXT: vcmp.s16 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <8 x i16> %src, zeroinitializer
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%0 = uitofp <8 x i1> %c to <8 x half>
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <8 x half> @sitofp_v8i1_v8f16(<8 x i16> %src) {
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; CHECK-LABEL: sitofp_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0xbc00
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; CHECK-NEXT: vcmp.s16 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <8 x i16> %src, zeroinitializer
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%0 = sitofp <8 x i1> %c to <8 x half>
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <8 x half> @fptoui_v8i1_v8f16(<8 x half> %src) {
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; CHECK-LABEL: fptoui_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0x3c00
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; CHECK-NEXT: vcmp.f16 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = fptoui <8 x half> %src to <8 x i1>
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%s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
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ret <8 x half> %s
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}
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define arm_aapcs_vfpcc <8 x half> @fptosi_v8i1_v8f16(<8 x half> %src) {
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; CHECK-LABEL: fptosi_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0x3c00
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; CHECK-NEXT: vcmp.f16 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = fptosi <8 x half> %src to <8 x i1>
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%s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
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ret <8 x half> %s
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}
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