896ece41e4
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
81 lines
2.5 KiB
LLVM
81 lines
2.5 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -arm-restrict-it | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC
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; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -arm-restrict-it -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC
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%struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* }
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%struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 }
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@FuncPtr = external hidden unnamed_addr global %struct.FF*
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@.str1 = external hidden unnamed_addr constant [6 x i8], align 4
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@G = external unnamed_addr global i32
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@.str2 = external hidden unnamed_addr constant [58 x i8], align 4
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@.str3 = external hidden unnamed_addr constant [58 x i8], align 4
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define i32 @test() nounwind optsize ssp {
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entry:
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; CHECK-LABEL: test:
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; CHECK: push
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; CHECK-NOT: push
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%block_size = alloca i32, align 4
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%block_count = alloca i32, align 4
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%index_cache = alloca i32, align 4
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store i32 0, i32* %index_cache, align 4
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%tmp = load i32, i32* @G, align 4
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%tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind
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switch i32 %tmp1, label %bb8 [
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i32 1, label %bb
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i32 536870913, label %bb4
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i32 536870914, label %bb6
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]
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bb:
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%tmp2 = load i32, i32* @G, align 4
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%tmp4 = icmp eq i32 %tmp2, 1
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br i1 %tmp4, label %bb1, label %bb8
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bb1:
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; CHECK: %entry
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; CHECK: it eq
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; CHECK-NEXT: ldreq
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; CHECK-NEXT: it eq
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; CHECK-NEXT: cmpeq
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; CHECK: %bb1
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%tmp5 = load i32, i32* %block_size, align 4
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%tmp6 = load i32, i32* %block_count, align 4
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%tmp7 = call %struct.FF* @Get() nounwind
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store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4
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%tmp10 = zext i32 %tmp6 to i64
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%tmp11 = zext i32 %tmp5 to i64
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%tmp12 = mul nsw i64 %tmp10, %tmp11
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%tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind
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br label %bb8
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bb4:
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; CHECK-PIC: cmp
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; CHECK-PIC: cmp
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; CHECK-PIC: cmp
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; CHECK-PIC: it eq
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; CHECK-PIC-NEXT: ldreq
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; CHECK-PIC-NEXT: it eq
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; CHECK-PIC-NEXT: cmpeq
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; CHECK-PIC-NEXT: beq
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; CHECK-PIC: %bb6
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; CHECK-PIC: mov
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ret i32 0
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bb6:
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ret i32 1
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bb8:
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ret i32 -1
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}
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declare i32 @printf(i8*, ...)
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declare %struct.FF* @Get()
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declare i32 @foo(i8*, i64, i32)
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declare i32 @bar(i32, i32, i32)
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