2d728bbff5
This patch adds a new intrinsic experimental.vector.reduce that takes a single vector and returns a vector of matching type but with the original lane order reversed. For example: ``` vector.reverse(<A,B,C,D>) ==> <D,C,B,A> ``` The new intrinsic supports fixed and scalable vectors types. The fixed-width vector relies on shufflevector to maintain existing behaviour. Scalable vector uses the new ISD node - VECTOR_REVERSE. This new intrinsic is one of the named shufflevector intrinsics proposed on the mailing-list in the RFC at [1]. Patch by Paul Walker (@paulwalker-arm). [1] https://lists.llvm.org/pipermail/llvm-dev/2020-November/146864.html Differential Revision: https://reviews.llvm.org/D94883
140 lines
4.7 KiB
LLVM
140 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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target triple = "x86_64-unknown-unknown"
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;
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; VECTOR_REVERSE
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;
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define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 {
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; CHECK-LABEL: reverse_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: movdqa %xmm0, %xmm2
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; CHECK-NEXT: punpcklbw %xmm1, %xmm
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; CHECK-NEXT: pshufd $78, %xmm2, %xmm2
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; CHECK-NEXT: pshuflw $27, %xmm2, %xmm2
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; CHECK-NEXT: pshufhw $27, %xmm2, %xmm2
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; CHECK-NEXT: punpckhbw %xmm1, %xmm0
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; CHECK-NEXT: pshufd $78, %xmm0, %xmm0
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; CHECK-NEXT: pshuflw $27, %xmm0, %xmm0
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; CHECK-NEXT: pshufhw $27, %xmm0, %xmm0
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; CHECK-NEXT: packuswb %xmm2, %xmm0
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; CHECK-NEXT: retq
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%res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a)
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ret <16 x i8> %res
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}
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define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 {
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; CHECK-LABEL: reverse_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd $78, %xmm0, %xmm
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; CHECK-NEXT: pshuflw $27, %xmm0, %xmm0
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; CHECK-NEXT: pshufhw $27, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a)
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ret <8 x i16> %res
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}
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define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: reverse_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd $27, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a)
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ret <4 x i32> %res
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}
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define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 {
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; CHECK-LABEL: reverse_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd $78, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a)
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ret <2 x i64> %res
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}
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define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
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; CHECK-LABEL: reverse_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shufps $27, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a)
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ret <4 x float> %res
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}
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define <2 x double> @reverse_v2f64(<2 x double> %a) #0 {
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; CHECK-LABEL: reverse_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shufps $78, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a)
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ret <2 x double> %res
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}
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; Verify promote type legalisation works as expected.
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define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
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; CHECK-LABEL: reverse_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa %xmm0, %xmm1
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; CHECK-NEXT: psrlw $8, %xmm1
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; CHECK-NEXT: psllw $8, %xmm0
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
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ret <2 x i8> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
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; CHECK-LABEL: reverse_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd $27, %xmm1, %xmm2
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; CHECK-NEXT: pshufd $27, %xmm0, %xmm1
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; CHECK-NEXT: movdqa %xmm2, %xmm0
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; CHECK-NEXT: retq
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%res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
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ret <8 x i32> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
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; CHECK-LABEL: reverse_v16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps %xmm1, %xmm4
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; CHECK-NEXT: movaps %xmm0, %xmm5
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; CHECK-NEXT: shufps $27, %xmm3, %xmm
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; CHECK-NEXT: shufps $27, %xmm2, %xmm2
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; CHECK-NEXT: shufps $27, %xmm1, %xmm4
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; CHECK-NEXT: shufps $27, %xmm0, %xmm5
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; CHECK-NEXT: movaps %xmm3, %xmm0
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; CHECK-NEXT: movaps %xmm2, %xmm1
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; CHECK-NEXT: movaps %xmm4, %xmm2
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; CHECK-NEXT: movaps %xmm5, %xmm3
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%res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
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ret <16 x float> %res
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}
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declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>)
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declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>)
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declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>)
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declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>)
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declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>)
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declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>)
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declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>)
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declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>)
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declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>)
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declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>)
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attributes #0 = { nounwind }
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