4841a225b7
Begin transitioning the X86 vector code to recognise sub(umax(a,b) ,b) or sub(a,umin(a,b)) USUBSAT patterns to make it more generic and available to all targets. This initial patch just moves the basic umin/umax patterns to DAG, removing some vector-only checks on the way - these are some of the patterns that the legalizer will try to expand back to so we can be reasonably relaxed about matching these pre-legalization. We can handle the trunc(sub(..))) variants as well, which helps with patterns where we were promoting to a wider type to detect overflow/saturation. The remaining x86 code requires some cleanup first - some of it isn't actually tested etc. I also need to resurrect D25987. Differential Revision: https://reviews.llvm.org/D96413
162 lines
4.8 KiB
LLVM
162 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64
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declare i4 @llvm.usub.sat.i4(i4, i4)
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declare i8 @llvm.usub.sat.i8(i8, i8)
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declare i16 @llvm.usub.sat.i16(i16, i16)
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declare i32 @llvm.usub.sat.i32(i32, i32)
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declare i64 @llvm.usub.sat.i64(i64, i64)
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declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; X86-LABEL: func:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: subl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cmovbl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: func:
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; X64: # %bb.0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subl %esi, %edi
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; X64-NEXT: cmovael %edi, %eax
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; X64-NEXT: retq
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%tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y)
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ret i32 %tmp
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; X86-LABEL: func2:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: subl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: sbbl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: cmovbl %ecx, %edx
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; X86-NEXT: cmovbl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: func2:
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; X64: # %bb.0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subq %rsi, %rdi
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; X64-NEXT: cmovaeq %rdi, %rax
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; X64-NEXT: retq
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%tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y)
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ret i64 %tmp
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}
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define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; X86-LABEL: func16:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: subw {{[0-9]+}}(%esp), %ax
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; X86-NEXT: cmovbl %ecx, %eax
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: func16:
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; X64: # %bb.0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subw %si, %di
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; X64-NEXT: cmovael %edi, %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y)
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ret i16 %tmp
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}
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define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; X86-LABEL: func8:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: subb {{[0-9]+}}(%esp), %al
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; X86-NEXT: movzbl %al, %eax
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; X86-NEXT: cmovbl %ecx, %eax
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; X86-NEXT: # kill: def $al killed $al killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: func8:
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; X64: # %bb.0:
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; X64-NEXT: xorl %ecx, %ecx
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; X64-NEXT: subb %sil, %dil
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: cmovbl %ecx, %eax
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y)
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ret i8 %tmp
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}
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define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
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; X86-LABEL: func3:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: subb {{[0-9]+}}(%esp), %al
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; X86-NEXT: movzbl %al, %eax
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; X86-NEXT: cmovbl %ecx, %eax
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; X86-NEXT: andl $15, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: func3:
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; X64: # %bb.0:
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; X64-NEXT: xorl %ecx, %ecx
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; X64-NEXT: subb %sil, %dil
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: cmovbl %ecx, %eax
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; X64-NEXT: andl $15, %eax
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; X64-NEXT: retq
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%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
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ret i4 %tmp
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}
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define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
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; X86-LABEL: vec:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: xorl %ebx, %ebx
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; X86-NEXT: subl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: cmovbl %ebx, %edi
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; X86-NEXT: subl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: cmovbl %ebx, %esi
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; X86-NEXT: subl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: cmovbl %ebx, %edx
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; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: cmovbl %ebx, %ecx
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; X86-NEXT: movl %ecx, 12(%eax)
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; X86-NEXT: movl %edx, 8(%eax)
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; X86-NEXT: movl %esi, 4(%eax)
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; X86-NEXT: movl %edi, (%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl $4
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;
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; X64-LABEL: vec:
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; X64: # %bb.0:
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; X64-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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; X64-NEXT: movdqa %xmm1, %xmm3
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; X64-NEXT: pxor %xmm2, %xmm3
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; X64-NEXT: pxor %xmm0, %xmm2
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; X64-NEXT: pcmpgtd %xmm3, %xmm2
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; X64-NEXT: psubd %xmm1, %xmm0
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; X64-NEXT: pand %xmm2, %xmm0
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; X64-NEXT: retq
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%tmp = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
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ret <4 x i32> %tmp
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}
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