57c3fe76a3
This build vector lowering pattern came up in D79886. I've tried to limit the improvement to cases where it looks clearly better to load, but we could remove the 'TODO' predicates already if we are willing to overlook some corner cases. Differential Revision: https://reviews.llvm.org/D80013
23 lines
742 B
LLVM
23 lines
742 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
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define <2 x i64> @PR25554(<2 x i64> %v0, <2 x i64> %v1) {
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; SSE-LABEL: PR25554:
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; SSE: # %bb.0:
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; SSE-NEXT: por {{.*}}(%rip), %xmm0
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; SSE-NEXT: paddq {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR25554:
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; AVX: # %bb.0:
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; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%c1 = or <2 x i64> %v0, <i64 1, i64 0>
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%c2 = add <2 x i64> %c1, <i64 0, i64 1>
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ret <2 x i64> %c2
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}
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