06c192d454
Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
89 lines
4.0 KiB
LLVM
89 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes
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; RUN: opt < %s -argpromotion -S | FileCheck %s
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; RUN: opt < %s -passes=argpromotion -S | FileCheck %s
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target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
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%struct.ss = type { i32, i64 }
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define internal void @f(%struct.ss* byval(%struct.ss) %b) nounwind {
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; CHECK-LABEL: define {{[^@]+}}@f
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; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]])
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
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; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0
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; CHECK-NEXT: store i32 [[B_0]], i32* [[DOT0]], align 4
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; CHECK-NEXT: [[DOT1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 1
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; CHECK-NEXT: store i64 [[B_1]], i64* [[DOT1]], align 4
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; CHECK-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
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; CHECK-NEXT: store i32 [[TMP2]], i32* [[TMP]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0
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%tmp1 = load i32, i32* %tmp, align 4
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%tmp2 = add i32 %tmp1, 1
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store i32 %tmp2, i32* %tmp, align 4
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ret void
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}
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define internal void @g(%struct.ss* byval(%struct.ss) align 32 %b) nounwind {
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; CHECK-LABEL: define {{[^@]+}}@g
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; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]])
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_SS:%.*]], align 32
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; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0
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; CHECK-NEXT: store i32 [[B_0]], i32* [[DOT0]], align 4
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; CHECK-NEXT: [[DOT1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 1
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; CHECK-NEXT: store i64 [[B_1]], i64* [[DOT1]], align 4
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; CHECK-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
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; CHECK-NEXT: store i32 [[TMP2]], i32* [[TMP]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0
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%tmp1 = load i32, i32* %tmp, align 4
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%tmp2 = add i32 %tmp1, 1
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store i32 %tmp2, i32* %tmp, align 4
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ret void
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}
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define i32 @main() nounwind {
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; CHECK-LABEL: define {{[^@]+}}@main()
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[S:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 0
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; CHECK-NEXT: store i32 1, i32* [[TMP1]], align 8
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1
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; CHECK-NEXT: store i64 2, i64* [[TMP4]], align 4
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; CHECK-NEXT: [[S_0:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 0
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; CHECK-NEXT: [[S_0_VAL:%.*]] = load i32, i32* [[S_0]], align 4
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; CHECK-NEXT: [[S_1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1
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; CHECK-NEXT: [[S_1_VAL:%.*]] = load i64, i64* [[S_1]], align 4
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; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]])
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; CHECK-NEXT: [[S_01:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 0
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; CHECK-NEXT: [[S_01_VAL:%.*]] = load i32, i32* [[S_01]], align 4
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; CHECK-NEXT: [[S_12:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1
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; CHECK-NEXT: [[S_12_VAL:%.*]] = load i64, i64* [[S_12]], align 4
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; CHECK-NEXT: call void @g(i32 [[S_01_VAL]], i64 [[S_12_VAL]])
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%S = alloca %struct.ss
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%tmp1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0
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store i32 1, i32* %tmp1, align 8
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%tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
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store i64 2, i64* %tmp4, align 4
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call void @f(%struct.ss* byval(%struct.ss) %S) nounwind
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call void @g(%struct.ss* byval(%struct.ss) %S) nounwind
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ret i32 0
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}
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