ef51eed37b
This builds on the restricted after initial revert form of D93906, and adds back support for breaking backedges of inner loops. It turns out the original invalidation logic wasn't quite right, specifically around the handling of LCSSA. When breaking the backedge of an inner loop, we can cause blocks which were in the outer loop only because they were also included in a sub-loop to be removed from both loops. This results in the exit block set for our original parent loop changing, and thus a need for new LCSSA phi nodes. This case happens when the inner loop has an exit block which is also an exit block of the parent, and there's a block in the child which reaches an exit to said block without also reaching an exit to the parent loop. (I'm describing this in terms of the immediate parent, but the problem is general for any transitive parent in the nest.) The approach implemented here involves a potentially expensive LCSSA rebuild. Perf testing during review didn't show anything concerning, but we may end up needing to revert this if anyone encounters a practical compile time issue. Differential Revision: https://reviews.llvm.org/D94378
138 lines
3.9 KiB
LLVM
138 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; TODO: Run under new PM after switch. The IR is the same but basic block labels are different.
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; RUN: opt -S -O2 -scev-cheap-expansion-budget=1024 %s -enable-new-pm=0 | FileCheck %s
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; See https://bugs.llvm.org/show_bug.cgi?id=45360
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; This is reduced from that (runnable) test.
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; The remainder operation is originally guarded, it never divides by zero.
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; Indvars should not make it execute unconditionally.
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-pc-linux-gnu"
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@f = dso_local global i32 0, align 4
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@a = dso_local global i32 0, align 4
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@d = dso_local global i32 0, align 4
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@c = dso_local global i32 0, align 4
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@b = dso_local global i32 0, align 4
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@e = dso_local global i32 0, align 4
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define dso_local i32 @main() {
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; CHECK-LABEL: @main(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[I6:%.*]] = load i32, i32* @a, align 4
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; CHECK-NEXT: [[I24:%.*]] = load i32, i32* @b, align 4
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; CHECK-NEXT: [[D_PROMOTED9:%.*]] = load i32, i32* @d, align 4
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; CHECK-NEXT: br label [[BB13_PREHEADER:%.*]]
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; CHECK: bb13.preheader:
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; CHECK-NEXT: [[I8_LCSSA10:%.*]] = phi i32 [ [[D_PROMOTED9]], [[BB:%.*]] ], [ [[I8:%.*]], [[BB19_PREHEADER:%.*]] ]
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; CHECK-NEXT: [[I8]] = and i32 [[I8_LCSSA10]], [[I6]]
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; CHECK-NEXT: [[I21:%.*]] = icmp eq i32 [[I8]], 0
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; CHECK-NEXT: br i1 [[I21]], label [[BB13_PREHEADER_BB27_THREAD_SPLIT_CRIT_EDGE:%.*]], label [[BB19_PREHEADER]]
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; CHECK: bb19.preheader:
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; CHECK-NEXT: [[I26:%.*]] = urem i32 [[I24]], [[I8]]
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; CHECK-NEXT: store i32 [[I26]], i32* @e, align 4
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; CHECK-NEXT: [[I30_NOT:%.*]] = icmp eq i32 [[I26]], 0
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; CHECK-NEXT: br i1 [[I30_NOT]], label [[BB32_LOOPEXIT:%.*]], label [[BB13_PREHEADER]]
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; CHECK: bb13.preheader.bb27.thread.split_crit_edge:
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; CHECK-NEXT: store i32 -1, i32* @f, align 4
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; CHECK-NEXT: store i32 0, i32* @d, align 4
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; CHECK-NEXT: store i32 0, i32* @c, align 4
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; CHECK-NEXT: br label [[BB32:%.*]]
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; CHECK: bb32.loopexit:
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; CHECK-NEXT: store i32 -1, i32* @f, align 4
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; CHECK-NEXT: store i32 [[I8]], i32* @d, align 4
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; CHECK-NEXT: br label [[BB32]]
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; CHECK: bb32:
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; CHECK-NEXT: [[C_SINK:%.*]] = phi i32* [ @c, [[BB32_LOOPEXIT]] ], [ @e, [[BB13_PREHEADER_BB27_THREAD_SPLIT_CRIT_EDGE]] ]
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; CHECK-NEXT: store i32 0, i32* [[C_SINK]], align 4
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; CHECK-NEXT: ret i32 0
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;
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bb:
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%i = alloca i32, align 4
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store i32 0, i32* %i, align 4
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br label %bb1
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bb1:
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store i32 0, i32* @f, align 4
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br label %bb2
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bb2:
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%i3 = load i32, i32* @f, align 4
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%i4 = icmp sge i32 %i3, 0
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br i1 %i4, label %bb5, label %bb12
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bb5:
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%i6 = load i32, i32* @a, align 4
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%i7 = load i32, i32* @d, align 4
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%i8 = and i32 %i7, %i6
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store i32 %i8, i32* @d, align 4
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br label %bb9
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bb9:
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%i10 = load i32, i32* @f, align 4
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%i11 = add nsw i32 %i10, -1
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store i32 %i11, i32* @f, align 4
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br label %bb2
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bb12:
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store i32 0, i32* @c, align 4
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br label %bb13
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bb13:
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%i14 = load i32, i32* @c, align 4
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%i15 = icmp sle i32 %i14, 0
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br i1 %i15, label %bb16, label %bb39
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bb16:
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%i17 = load i32, i32* @f, align 4
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%i18 = icmp ne i32 %i17, 0
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br i1 %i18, label %bb19, label %bb34
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bb19:
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%i20 = load i32, i32* @d, align 4
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%i21 = icmp eq i32 %i20, 0
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br i1 %i21, label %bb22, label %bb23
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bb22:
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br label %bb27
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bb23:
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%i24 = load i32, i32* @b, align 4
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%i25 = load i32, i32* @d, align 4
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%i26 = urem i32 %i24, %i25
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br label %bb27
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bb27:
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%i28 = phi i32 [ 0, %bb22 ], [ %i26, %bb23 ]
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store i32 %i28, i32* @e, align 4
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%i29 = load i32, i32* @e, align 4
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%i30 = icmp ne i32 %i29, 0
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br i1 %i30, label %bb31, label %bb32
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bb31:
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br label %bb33
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bb32:
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ret i32 0
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bb33:
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br label %bb35
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bb34:
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store i32 0, i32* @d, align 4
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br label %bb35
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bb35:
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br label %bb36
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bb36:
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%i37 = load i32, i32* @c, align 4
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%i38 = add nsw i32 %i37, 1
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store i32 %i38, i32* @c, align 4
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br label %bb13
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bb39:
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br label %bb1
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}
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