8393b9fd1f
Instructions defined in the original inner loop preheader may depend on values defined in the outer loop header, but the inner loop header will become the entry block in the loop nest. Move the instructions from the preheader to the outer loop header, so we do not break dominance. We also have to check for unsafe instructions in the preheader. If there are no unsafe instructions, all instructions should be movable. Currently we move all instructions except the terminator and rely on LICM to hoist out invariant instructions later. Fixes PR45743
142 lines
6.4 KiB
LLVM
142 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-interchange -S %s | FileCheck %s
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@global = external local_unnamed_addr global [2 x [10 x i32]], align 16
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; We need to move %tmp4 from the inner loop pre header to the outer loop header
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; before interchanging.
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define void @test1() local_unnamed_addr #0 {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[INNER_PH:%.*]]
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; CHECK: outer.header.preheader:
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; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
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; CHECK: outer.header:
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; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
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; CHECK-NEXT: [[INNER_RED:%.*]] = phi i32 [ [[OUTER_RED:%.*]], [[OUTER_HEADER_PREHEADER]] ], [ [[RED_NEXT:%.*]], [[OUTER_LATCH]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = add nsw i64 [[OUTER_IV]], 9
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; CHECK-NEXT: br label [[INNER_SPLIT1:%.*]]
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; CHECK: inner.ph:
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; CHECK-NEXT: br label [[INNER:%.*]]
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; CHECK: inner:
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; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[INNER_PH]] ], [ [[TMP0:%.*]], [[INNER_SPLIT:%.*]] ]
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; CHECK-NEXT: [[OUTER_RED]] = phi i32 [ [[RED_NEXT_LCSSA:%.*]], [[INNER_SPLIT]] ], [ 0, [[INNER_PH]] ]
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; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
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; CHECK: inner.split1:
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [2 x [10 x i32]], [2 x [10 x i32]]* @global, i64 0, i64 [[INNER_IV]], i64 [[TMP4]]
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; CHECK-NEXT: store i32 0, i32* [[PTR]], align 4
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; CHECK-NEXT: [[RED_NEXT]] = or i32 [[INNER_RED]], 20
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; CHECK-NEXT: [[INNER_IV_NEXT:%.*]] = add nsw i64 [[INNER_IV]], 1
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; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 400
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; CHECK-NEXT: br label [[OUTER_LATCH]]
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; CHECK: inner.split:
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; CHECK-NEXT: [[RED_NEXT_LCSSA]] = phi i32 [ [[RED_NEXT]], [[OUTER_LATCH]] ]
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; CHECK-NEXT: [[TMP0]] = add nsw i64 [[INNER_IV]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 400
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; CHECK-NEXT: br i1 [[TMP1]], label [[EXIT:%.*]], label [[INNER]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
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; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i64 [[OUTER_IV_NEXT]], 400
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; CHECK-NEXT: br i1 [[EC_2]], label [[INNER_SPLIT]], label [[OUTER_HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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bb:
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br label %outer.header
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outer.header: ; preds = %bb11, %bb
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%outer.iv = phi i64 [ 0, %bb ], [ %outer.iv.next, %outer.latch ]
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%outer.red = phi i32 [ 0, %bb ], [ %red.next.lcssa, %outer.latch ]
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br label %inner.ph
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inner.ph: ; preds = %bb1
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%tmp4 = add nsw i64 %outer.iv, 9
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br label %inner
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inner: ; preds = %bb5, %bb3
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%inner.iv = phi i64 [ 0, %inner.ph ], [ %inner.iv.next, %inner ]
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%inner.red = phi i32 [ %outer.red, %inner.ph ], [ %red.next, %inner ]
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%ptr = getelementptr inbounds [2 x [10 x i32]], [2 x [10 x i32]]* @global, i64 0, i64 %inner.iv, i64 %tmp4
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store i32 0, i32* %ptr
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%red.next = or i32 %inner.red, 20
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%inner.iv.next = add nsw i64 %inner.iv, 1
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%ec.1 = icmp eq i64 %inner.iv.next, 400
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br i1 %ec.1, label %outer.latch, label %inner
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outer.latch: ; preds = %bb5
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%red.next.lcssa = phi i32 [ %red.next, %inner ]
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%outer.iv.next = add nsw i64 %outer.iv, 1
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%ec.2 = icmp eq i64 %outer.iv.next, 400
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br i1 %ec.2, label %exit, label %outer.header
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exit: ; preds = %bb11
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ret void
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}
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declare void @side_effect()
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; Cannot interchange, as the inner loop preheader contains a call to a function
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; with side effects.
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define void @test2() {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
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; CHECK: outer.header:
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; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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; CHECK-NEXT: [[OUTER_RED:%.*]] = phi i32 [ 0, [[BB]] ], [ [[RED_NEXT_LCSSA:%.*]], [[OUTER_LATCH]] ]
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; CHECK-NEXT: br label [[INNER_PH:%.*]]
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; CHECK: inner.ph:
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; CHECK-NEXT: [[TMP4:%.*]] = add nsw i64 [[OUTER_IV]], 9
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; CHECK-NEXT: call void @side_effect()
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; CHECK-NEXT: br label [[INNER:%.*]]
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; CHECK: inner:
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; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[INNER_PH]] ], [ [[INNER_IV_NEXT:%.*]], [[INNER]] ]
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; CHECK-NEXT: [[INNER_RED:%.*]] = phi i32 [ [[OUTER_RED]], [[INNER_PH]] ], [ [[RED_NEXT:%.*]], [[INNER]] ]
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [2 x [10 x i32]], [2 x [10 x i32]]* @global, i64 0, i64 [[INNER_IV]], i64 [[TMP4]]
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; CHECK-NEXT: store i32 0, i32* [[PTR]], align 4
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; CHECK-NEXT: [[RED_NEXT]] = or i32 [[INNER_RED]], 20
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; CHECK-NEXT: [[INNER_IV_NEXT]] = add nsw i64 [[INNER_IV]], 1
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; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 400
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; CHECK-NEXT: br i1 [[EC_1]], label [[OUTER_LATCH]], label [[INNER]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[RED_NEXT_LCSSA]] = phi i32 [ [[RED_NEXT]], [[INNER]] ]
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; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
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; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i64 [[OUTER_IV_NEXT]], 400
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; CHECK-NEXT: br i1 [[EC_2]], label [[EXIT:%.*]], label [[OUTER_HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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bb:
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br label %outer.header
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outer.header: ; preds = %bb11, %bb
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%outer.iv = phi i64 [ 0, %bb ], [ %outer.iv.next, %outer.latch ]
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%outer.red = phi i32 [ 0, %bb ], [ %red.next.lcssa, %outer.latch ]
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br label %inner.ph
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inner.ph: ; preds = %bb1
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%tmp4 = add nsw i64 %outer.iv, 9
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call void @side_effect()
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br label %inner
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inner: ; preds = %bb5, %bb3
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%inner.iv = phi i64 [ 0, %inner.ph ], [ %inner.iv.next, %inner ]
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%inner.red = phi i32 [ %outer.red, %inner.ph ], [ %red.next, %inner ]
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%ptr = getelementptr inbounds [2 x [10 x i32]], [2 x [10 x i32]]* @global, i64 0, i64 %inner.iv, i64 %tmp4
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store i32 0, i32* %ptr
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%red.next = or i32 %inner.red, 20
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%inner.iv.next = add nsw i64 %inner.iv, 1
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%ec.1 = icmp eq i64 %inner.iv.next, 400
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br i1 %ec.1, label %outer.latch, label %inner
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outer.latch: ; preds = %bb5
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%red.next.lcssa = phi i32 [ %red.next, %inner ]
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%outer.iv.next = add nsw i64 %outer.iv, 1
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%ec.2 = icmp eq i64 %outer.iv.next, 400
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br i1 %ec.2, label %exit, label %outer.header
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exit: ; preds = %bb11
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ret void
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}
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