d4d4ceeb8f
This patch updates IRBuilder::CreateMaskedGather/Scatter to work with ScalableVectorType and adds isLegalMaskedGather/Scatter functions to AArch64TargetTransformInfo. In addition I've fixed up isLegalMaskedLoad/Store to return true for supported scalar types, since this is what the vectorizer asks for. In LoopVectorize.cpp I've changed LoopVectorizationCostModel::getInterleaveGroupCost to return an invalid cost for scalable vectors, since currently this relies upon using shuffle vector for reversing vectors. In addition, in LoopVectorizationCostModel::setCostBasedWideningDecision I have assumed that the cost of scalarising memory ops is infinitely expensive. I have added some simple masked load/store and gather/scatter tests, including cases where we use gathers and scatters for conditional invariant loads and stores. Differential Revision: https://reviews.llvm.org/D95350
83 lines
4.0 KiB
LLVM
83 lines
4.0 KiB
LLVM
; RUN: opt -loop-vectorize -dce -instcombine -mtriple aarch64-linux-gnu -mattr=+sve -S %s -o - | FileCheck %s
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define void @mloadstore_f32(float* noalias nocapture %a, float* noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @mloadstore_f32
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; CHECK: vector.body:
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; CHECK: %[[LOAD1:.*]] = load <vscale x 4 x float>, <vscale x 4 x float>*
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; CHECK-NEXT: %[[MASK:.*]] = fcmp ogt <vscale x 4 x float> %[[LOAD1]],
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; CHECK-NEXT: %[[GEPA:.*]] = getelementptr inbounds float, float* %a,
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; CHECK-NEXT: %[[MLOAD_PTRS:.*]] = bitcast float* %[[GEPA]] to <vscale x 4 x float>*
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; CHECK-NEXT: %[[LOAD2:.*]] = call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0nxv4f32(<vscale x 4 x float>* %[[MLOAD_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]]
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; CHECK-NEXT: %[[FADD:.*]] = fadd <vscale x 4 x float> %[[LOAD1]], %[[LOAD2]]
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; CHECK-NEXT: %[[MSTORE_PTRS:.*]] = bitcast float* %[[GEPA]] to <vscale x 4 x float>*
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; CHECK-NEXT: call void @llvm.masked.store.nxv4f32.p0nxv4f32(<vscale x 4 x float> %[[FADD]], <vscale x 4 x float>* %[[MSTORE_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]])
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.inc
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%i.011 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds float, float* %b, i64 %i.011
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%0 = load float, float* %arrayidx, align 4
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%cmp1 = fcmp ogt float %0, 0.000000e+00
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br i1 %cmp1, label %if.then, label %for.inc
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if.then: ; preds = %for.body
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%arrayidx3 = getelementptr inbounds float, float* %a, i64 %i.011
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%1 = load float, float* %arrayidx3, align 4
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%add = fadd float %0, %1
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store float %add, float* %arrayidx3, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%inc = add nuw nsw i64 %i.011, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !0
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exit: ; preds = %for.inc
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ret void
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}
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define void @mloadstore_i32(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @mloadstore_i32
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; CHECK: vector.body:
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; CHECK: %[[LOAD1:.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>*
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; CHECK-NEXT: %[[MASK:.*]] = icmp ne <vscale x 4 x i32> %[[LOAD1]],
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; CHECK-NEXT: %[[GEPA:.*]] = getelementptr inbounds i32, i32* %a,
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; CHECK-NEXT: %[[MLOAD_PTRS:.*]] = bitcast i32* %[[GEPA]] to <vscale x 4 x i32>*
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; CHECK-NEXT: %[[LOAD2:.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %[[MLOAD_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]]
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; CHECK-NEXT: %[[FADD:.*]] = add <vscale x 4 x i32> %[[LOAD1]], %[[LOAD2]]
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; CHECK-NEXT: %[[MSTORE_PTRS:.*]] = bitcast i32* %[[GEPA]] to <vscale x 4 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %[[FADD]], <vscale x 4 x i32>* %[[MSTORE_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]])
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.inc
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%i.011 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %b, i64 %i.011
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%0 = load i32, i32* %arrayidx, align 4
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%cmp1 = icmp ne i32 %0, 0
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br i1 %cmp1, label %if.then, label %for.inc
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if.then: ; preds = %for.body
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%arrayidx3 = getelementptr inbounds i32, i32* %a, i64 %i.011
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%1 = load i32, i32* %arrayidx3, align 4
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%add = add i32 %0, %1
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store i32 %add, i32* %arrayidx3, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%inc = add nuw nsw i64 %i.011, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !0
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exit: ; preds = %for.inc
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ret void
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}
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!0 = distinct !{!0, !1, !2, !3, !4, !5}
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!1 = !{!"llvm.loop.mustprogress"}
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!2 = !{!"llvm.loop.vectorize.width", i32 4}
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!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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!4 = !{!"llvm.loop.interleave.count", i32 1}
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!5 = !{!"llvm.loop.vectorize.enable", i1 true}
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