79b1b4a581
The vector reduction intrinsics started life as experimental ops, so backend support was lacking. As part of promoting them to 1st-class intrinsics, however, codegen support was added/improved: D58015 D90247 So I think it is safe to now remove this complication from IR. Note that we still have an IR-level codegen expansion pass for these as discussed in D95690. Removing that is another step in simplifying the logic. Also note that x86 was already unconditionally forming reductions in IR, so there should be no difference for x86. I spot checked a couple of the tests here by running them through opt+llc and did not see any asm diffs. If we do find functional differences for other targets, it should be possible to (at least temporarily) restore the shuffle IR with the ExpandReductions IR pass. Differential Revision: https://reviews.llvm.org/D96552
59 lines
2.6 KiB
LLVM
59 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -vectorizer-maximize-bandwidth -mtriple=powerpc64le-- -S \
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; RUN: -targetlibinfo -loop-simplify -loop-rotate -loop-vectorize \
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; RUN: -instcombine -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -force-vector-interleave=1 < %s | FileCheck %s
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define dso_local double @test(float* %Arr) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[INDEX]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, float* [[ARR:%.*]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[TMP1]] to <2 x float>*
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = fpext <2 x float> [[WIDE_LOAD]] to <2 x double>
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; CHECK-NEXT: [[TMP4:%.*]] = call fast <2 x double> @__sind2_massv(<2 x double> [[TMP3]])
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; CHECK-NEXT: [[TMP5]] = fadd fast <2 x double> [[VEC_PHI]], [[TMP4]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
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; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP7:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[TMP5]])
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; CHECK-NEXT: ret double [[TMP7]]
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;
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entry:
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br label %for.cond
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for.cond:
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%Sum.0 = phi double [ 0.000000e+00, %entry ], [ %add, %for.inc ]
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %i.0, 128
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %i.0 to i64
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%arrayidx = getelementptr inbounds float, float* %Arr, i64 %idxprom
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%0 = load float, float* %arrayidx, align 4
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%conv = fpext float %0 to double
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%1 = call fast double @llvm.sin.f64(double %conv) #1
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%add = fadd fast double %Sum.0, %1
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end:
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ret double %Sum.0
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}
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declare double @llvm.sin.f64(double) #0
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declare <2 x double> @__sind2_massv(<2 x double>) #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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attributes #1 = { "vector-function-abi-variant"="_ZGV_LLVM_N2v_llvm.sin.f64(__sind2_massv)" }
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