8c11bc0cd0
An irreducible SCC is one which has multiple "header" blocks, i.e., blocks with control-flow edges incident from outside the SCC. This pass converts an irreducible SCC into a natural loop by introducing a single new header block and redirecting all the edges on the original headers to this new block. This is a useful workaround for a limitation in the structurizer which, which produces incorrect control flow in the presence of irreducible regions. The AMDGPU backend provides an option to enable this pass before the structurizer, which may eventually be enabled by default. Reviewed By: nhaehnle Differential Revision: https://reviews.llvm.org/D77198 This restores commit 2ada8e2525dd2653f30c8696a27162a3b1647d66. Originally reverted with commit 44e09b59b869a91bf47d76e8bc569d9ee91ad145.
61 lines
2.2 KiB
LLVM
61 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -fix-irreducible -structurizecfg -S | FileCheck %s
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; Both B1 and B4 are headers of an irreducible cycle. But in the
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; structurized version, B1 dominates B4. The program is structurized
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; correctly when the irreducible cycle is fixed.
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define void @irreducible(i1 %PredEntry, i1 %PredB1, i1 %PredB2, i1 %PredB3, i1 %PredB4)
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; CHECK-LABEL: @irreducible(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[PREDB2_INV:%.*]] = xor i1 [[PREDB2:%.*]], true
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; CHECK-NEXT: [[PREDB1_INV:%.*]] = xor i1 [[PREDB1:%.*]], true
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; CHECK-NEXT: br label [[IRR_GUARD:%.*]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ [[PREDB4:%.*]], [[B4:%.*]] ], [ false, [[IRR_GUARD]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ false, [[B4]] ], [ true, [[IRR_GUARD]] ]
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; CHECK-NEXT: br i1 [[TMP1]], label [[B1:%.*]], label [[FLOW1:%.*]]
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; CHECK: B1:
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; CHECK-NEXT: br label [[FLOW1]]
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; CHECK: Flow1:
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; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ [[PREDB1_INV]], [[B1]] ], [ [[TMP0]], [[FLOW:%.*]] ]
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; CHECK-NEXT: br i1 [[TMP2]], label [[B2:%.*]], label [[FLOW2:%.*]]
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; CHECK: B2:
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; CHECK-NEXT: br i1 [[PREDB2_INV]], label [[B3:%.*]], label [[FLOW3:%.*]]
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; CHECK: Flow2:
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; CHECK-NEXT: [[TMP3:%.*]] = phi i1 [ [[TMP4:%.*]], [[FLOW3]] ], [ true, [[FLOW1]] ]
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; CHECK-NEXT: br i1 [[TMP3]], label [[EXIT:%.*]], label [[IRR_GUARD]]
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; CHECK: B3:
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; CHECK-NEXT: br label [[FLOW3]]
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; CHECK: B4:
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: Flow3:
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; CHECK-NEXT: [[TMP4]] = phi i1 [ false, [[B3]] ], [ true, [[B2]] ]
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; CHECK-NEXT: br label [[FLOW2]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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; CHECK: irr.guard:
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; CHECK-NEXT: [[GUARD_B1:%.*]] = phi i1 [ [[PREDENTRY:%.*]], [[ENTRY:%.*]] ], [ [[PREDB3:%.*]], [[FLOW2]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = xor i1 [[GUARD_B1]], true
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; CHECK-NEXT: br i1 [[TMP5]], label [[B4]], label [[FLOW]]
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;
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{
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entry:
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br i1 %PredEntry, label %B1, label %B4
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B1:
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br i1 %PredB1, label %exit, label %B2
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B2:
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br i1 %PredB2, label %exit, label %B3
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B3:
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br i1 %PredB3, label %B1, label %B4
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B4:
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br i1 %PredB4, label %B2, label %exit
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exit:
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ret void
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}
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