a57def30f5
Adding the ability to index the base address brings these operations closer to the transfer read and write semantics (with lowering advantages), ensures more consistent use in vector MLIR code (easier to read), and reduces the amount of code duplication to lower memrefs into base addresses considerably (making codegen less error-prone). Reviewed By: ThomasRaoux Differential Revision: https://reviews.llvm.org/D94278
98 lines
3.7 KiB
MLIR
98 lines
3.7 KiB
MLIR
// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm -convert-std-to-llvm | \
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// RUN: mlir-cpu-runner -e entry -entry-point-result=void \
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// RUN: -shared-libs=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
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// RUN: FileCheck %s
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func @expand16(%base: memref<?xf32>,
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%mask: vector<16xi1>,
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%pass_thru: vector<16xf32>) -> vector<16xf32> {
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%c0 = constant 0: index
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%e = vector.expandload %base[%c0], %mask, %pass_thru
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: memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
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return %e : vector<16xf32>
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}
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func @expand16_at8(%base: memref<?xf32>,
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%mask: vector<16xi1>,
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%pass_thru: vector<16xf32>) -> vector<16xf32> {
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%c8 = constant 8: index
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%e = vector.expandload %base[%c8], %mask, %pass_thru
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: memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
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return %e : vector<16xf32>
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}
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func @entry() {
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// Set up memory.
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%c0 = constant 0: index
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%c1 = constant 1: index
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%c16 = constant 16: index
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%A = alloc(%c16) : memref<?xf32>
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scf.for %i = %c0 to %c16 step %c1 {
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%i32 = index_cast %i : index to i32
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%fi = sitofp %i32 : i32 to f32
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store %fi, %A[%i] : memref<?xf32>
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}
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// Set up pass thru vector.
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%u = constant -7.0: f32
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%v = constant 7.7: f32
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%pass = vector.broadcast %u : f32 to vector<16xf32>
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// Set up masks.
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%f = constant 0: i1
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%t = constant 1: i1
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%none = vector.constant_mask [0] : vector<16xi1>
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%all = vector.constant_mask [16] : vector<16xi1>
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%some1 = vector.constant_mask [4] : vector<16xi1>
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%0 = vector.insert %f, %some1[0] : i1 into vector<16xi1>
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%1 = vector.insert %t, %0[7] : i1 into vector<16xi1>
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%2 = vector.insert %t, %1[11] : i1 into vector<16xi1>
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%3 = vector.insert %t, %2[13] : i1 into vector<16xi1>
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%some2 = vector.insert %t, %3[15] : i1 into vector<16xi1>
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%some3 = vector.insert %f, %some2[2] : i1 into vector<16xi1>
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//
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// Expanding load tests.
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//
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%e1 = call @expand16(%A, %none, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %e1 : vector<16xf32>
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// CHECK: ( -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7 )
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%e2 = call @expand16(%A, %all, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %e2 : vector<16xf32>
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// CHECK-NEXT: ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 )
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%e3 = call @expand16(%A, %some1, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %e3 : vector<16xf32>
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// CHECK-NEXT: ( 0, 1, 2, 3, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7 )
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%e4 = call @expand16(%A, %some2, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %e4 : vector<16xf32>
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// CHECK-NEXT: ( -7, 0, 1, 2, -7, -7, -7, 3, -7, -7, -7, 4, -7, 5, -7, 6 )
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%e5 = call @expand16(%A, %some3, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %e5 : vector<16xf32>
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// CHECK-NEXT: ( -7, 0, -7, 1, -7, -7, -7, 2, -7, -7, -7, 3, -7, 4, -7, 5 )
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%4 = vector.insert %v, %pass[1] : f32 into vector<16xf32>
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%5 = vector.insert %v, %4[2] : f32 into vector<16xf32>
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%alt_pass = vector.insert %v, %5[14] : f32 into vector<16xf32>
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%e6 = call @expand16(%A, %some3, %alt_pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %e6 : vector<16xf32>
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// CHECK-NEXT: ( -7, 0, 7.7, 1, -7, -7, -7, 2, -7, -7, -7, 3, -7, 4, 7.7, 5 )
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%e7 = call @expand16_at8(%A, %some1, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %e7 : vector<16xf32>
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// CHECK-NEXT: ( 8, 9, 10, 11, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7 )
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return
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}
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