This patch adds the 'vector.load' and 'vector.store' ops to the Vector dialect [1]. These operations model *contiguous* vector loads and stores from/to memory. Their semantics are similar to the 'affine.vector_load' and 'affine.vector_store' counterparts but without the affine constraints. The most relevant feature is that these new vector operations may perform a vector load/store on memrefs with a non-vector element type, unlike 'std.load' and 'std.store' ops. This opens the representation to model more generic vector load/store scenarios: unaligned vector loads/stores, perform scalar and vector memory access on the same memref, decouple memory allocation constraints from memory accesses, etc [1]. These operations will also facilitate the progressive lowering of both Affine vector loads/stores and Vector transfer reads/writes for those that read/write contiguous slices from/to memory. In particular, this patch adds the 'vector.load' and 'vector.store' ops to the Vector dialect, implements their lowering to the LLVM dialect, and changes the lowering of 'affine.vector_load' and 'affine.vector_store' ops to the new vector ops. The lowering of Vector transfer reads/writes will be implemented in the future, probably as an independent pass. The API of 'vector.maskedload' and 'vector.maskedstore' has also been changed slightly to align it with the transfer read/write ops and the vector new ops. This will improve reusability among all these operations. For example, the lowering of 'vector.load', 'vector.store', 'vector.maskedload' and 'vector.maskedstore' to the LLVM dialect is implemented with a single template conversion pattern. [1] https://llvm.discourse.group/t/memref-type-and-data-layout/ Reviewed By: nicolasvasilache Differential Revision: https://reviews.llvm.org/D96185
794 lines
31 KiB
C++
794 lines
31 KiB
C++
//===- AffineToStandard.cpp - Lower affine constructs to primitives -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file lowers affine constructs (If and For statements, AffineApply
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// operations) within a function into their standard If and For equivalent ops.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/AffineToStandard/AffineToStandard.h"
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#include "../PassDetail.h"
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#include "mlir/Dialect/Affine/IR/AffineOps.h"
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#include "mlir/Dialect/SCF/SCF.h"
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#include "mlir/Dialect/StandardOps/IR/Ops.h"
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#include "mlir/Dialect/Vector/VectorOps.h"
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#include "mlir/IR/AffineExprVisitor.h"
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#include "mlir/IR/BlockAndValueMapping.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/IntegerSet.h"
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#include "mlir/IR/MLIRContext.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/Passes.h"
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using namespace mlir;
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using namespace mlir::vector;
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namespace {
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/// Visit affine expressions recursively and build the sequence of operations
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/// that correspond to it. Visitation functions return an Value of the
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/// expression subtree they visited or `nullptr` on error.
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class AffineApplyExpander
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: public AffineExprVisitor<AffineApplyExpander, Value> {
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public:
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/// This internal class expects arguments to be non-null, checks must be
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/// performed at the call site.
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AffineApplyExpander(OpBuilder &builder, ValueRange dimValues,
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ValueRange symbolValues, Location loc)
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: builder(builder), dimValues(dimValues), symbolValues(symbolValues),
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loc(loc) {}
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template <typename OpTy> Value buildBinaryExpr(AffineBinaryOpExpr expr) {
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auto lhs = visit(expr.getLHS());
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auto rhs = visit(expr.getRHS());
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if (!lhs || !rhs)
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return nullptr;
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auto op = builder.create<OpTy>(loc, lhs, rhs);
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return op.getResult();
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}
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Value visitAddExpr(AffineBinaryOpExpr expr) {
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return buildBinaryExpr<AddIOp>(expr);
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}
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Value visitMulExpr(AffineBinaryOpExpr expr) {
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return buildBinaryExpr<MulIOp>(expr);
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}
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/// Euclidean modulo operation: negative RHS is not allowed.
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/// Remainder of the euclidean integer division is always non-negative.
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///
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/// Implemented as
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///
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/// a mod b =
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/// let remainder = srem a, b;
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/// negative = a < 0 in
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/// select negative, remainder + b, remainder.
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Value visitModExpr(AffineBinaryOpExpr expr) {
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auto rhsConst = expr.getRHS().dyn_cast<AffineConstantExpr>();
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if (!rhsConst) {
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emitError(
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loc,
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"semi-affine expressions (modulo by non-const) are not supported");
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return nullptr;
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}
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if (rhsConst.getValue() <= 0) {
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emitError(loc, "modulo by non-positive value is not supported");
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return nullptr;
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}
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auto lhs = visit(expr.getLHS());
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auto rhs = visit(expr.getRHS());
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assert(lhs && rhs && "unexpected affine expr lowering failure");
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Value remainder = builder.create<SignedRemIOp>(loc, lhs, rhs);
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Value zeroCst = builder.create<ConstantIndexOp>(loc, 0);
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Value isRemainderNegative =
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builder.create<CmpIOp>(loc, CmpIPredicate::slt, remainder, zeroCst);
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Value correctedRemainder = builder.create<AddIOp>(loc, remainder, rhs);
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Value result = builder.create<SelectOp>(loc, isRemainderNegative,
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correctedRemainder, remainder);
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return result;
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}
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/// Floor division operation (rounds towards negative infinity).
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///
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/// For positive divisors, it can be implemented without branching and with a
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/// single division operation as
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///
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/// a floordiv b =
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/// let negative = a < 0 in
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/// let absolute = negative ? -a - 1 : a in
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/// let quotient = absolute / b in
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/// negative ? -quotient - 1 : quotient
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Value visitFloorDivExpr(AffineBinaryOpExpr expr) {
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auto rhsConst = expr.getRHS().dyn_cast<AffineConstantExpr>();
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if (!rhsConst) {
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emitError(
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loc,
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"semi-affine expressions (division by non-const) are not supported");
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return nullptr;
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}
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if (rhsConst.getValue() <= 0) {
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emitError(loc, "division by non-positive value is not supported");
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return nullptr;
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}
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auto lhs = visit(expr.getLHS());
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auto rhs = visit(expr.getRHS());
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assert(lhs && rhs && "unexpected affine expr lowering failure");
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Value zeroCst = builder.create<ConstantIndexOp>(loc, 0);
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Value noneCst = builder.create<ConstantIndexOp>(loc, -1);
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Value negative =
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builder.create<CmpIOp>(loc, CmpIPredicate::slt, lhs, zeroCst);
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Value negatedDecremented = builder.create<SubIOp>(loc, noneCst, lhs);
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Value dividend =
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builder.create<SelectOp>(loc, negative, negatedDecremented, lhs);
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Value quotient = builder.create<SignedDivIOp>(loc, dividend, rhs);
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Value correctedQuotient = builder.create<SubIOp>(loc, noneCst, quotient);
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Value result =
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builder.create<SelectOp>(loc, negative, correctedQuotient, quotient);
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return result;
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}
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/// Ceiling division operation (rounds towards positive infinity).
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///
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/// For positive divisors, it can be implemented without branching and with a
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/// single division operation as
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///
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/// a ceildiv b =
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/// let negative = a <= 0 in
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/// let absolute = negative ? -a : a - 1 in
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/// let quotient = absolute / b in
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/// negative ? -quotient : quotient + 1
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Value visitCeilDivExpr(AffineBinaryOpExpr expr) {
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auto rhsConst = expr.getRHS().dyn_cast<AffineConstantExpr>();
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if (!rhsConst) {
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emitError(loc) << "semi-affine expressions (division by non-const) are "
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"not supported";
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return nullptr;
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}
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if (rhsConst.getValue() <= 0) {
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emitError(loc, "division by non-positive value is not supported");
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return nullptr;
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}
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auto lhs = visit(expr.getLHS());
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auto rhs = visit(expr.getRHS());
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assert(lhs && rhs && "unexpected affine expr lowering failure");
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Value zeroCst = builder.create<ConstantIndexOp>(loc, 0);
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Value oneCst = builder.create<ConstantIndexOp>(loc, 1);
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Value nonPositive =
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builder.create<CmpIOp>(loc, CmpIPredicate::sle, lhs, zeroCst);
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Value negated = builder.create<SubIOp>(loc, zeroCst, lhs);
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Value decremented = builder.create<SubIOp>(loc, lhs, oneCst);
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Value dividend =
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builder.create<SelectOp>(loc, nonPositive, negated, decremented);
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Value quotient = builder.create<SignedDivIOp>(loc, dividend, rhs);
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Value negatedQuotient = builder.create<SubIOp>(loc, zeroCst, quotient);
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Value incrementedQuotient = builder.create<AddIOp>(loc, quotient, oneCst);
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Value result = builder.create<SelectOp>(loc, nonPositive, negatedQuotient,
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incrementedQuotient);
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return result;
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}
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Value visitConstantExpr(AffineConstantExpr expr) {
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auto valueAttr =
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builder.getIntegerAttr(builder.getIndexType(), expr.getValue());
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auto op =
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builder.create<ConstantOp>(loc, builder.getIndexType(), valueAttr);
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return op.getResult();
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}
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Value visitDimExpr(AffineDimExpr expr) {
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assert(expr.getPosition() < dimValues.size() &&
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"affine dim position out of range");
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return dimValues[expr.getPosition()];
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}
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Value visitSymbolExpr(AffineSymbolExpr expr) {
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assert(expr.getPosition() < symbolValues.size() &&
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"symbol dim position out of range");
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return symbolValues[expr.getPosition()];
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}
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private:
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OpBuilder &builder;
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ValueRange dimValues;
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ValueRange symbolValues;
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Location loc;
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};
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} // namespace
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/// Create a sequence of operations that implement the `expr` applied to the
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/// given dimension and symbol values.
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mlir::Value mlir::expandAffineExpr(OpBuilder &builder, Location loc,
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AffineExpr expr, ValueRange dimValues,
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ValueRange symbolValues) {
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return AffineApplyExpander(builder, dimValues, symbolValues, loc).visit(expr);
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}
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/// Create a sequence of operations that implement the `affineMap` applied to
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/// the given `operands` (as it it were an AffineApplyOp).
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Optional<SmallVector<Value, 8>> mlir::expandAffineMap(OpBuilder &builder,
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Location loc,
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AffineMap affineMap,
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ValueRange operands) {
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auto numDims = affineMap.getNumDims();
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auto expanded = llvm::to_vector<8>(
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llvm::map_range(affineMap.getResults(),
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[numDims, &builder, loc, operands](AffineExpr expr) {
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return expandAffineExpr(builder, loc, expr,
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operands.take_front(numDims),
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operands.drop_front(numDims));
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}));
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if (llvm::all_of(expanded, [](Value v) { return v; }))
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return expanded;
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return None;
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}
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/// Given a range of values, emit the code that reduces them with "min" or "max"
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/// depending on the provided comparison predicate. The predicate defines which
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/// comparison to perform, "lt" for "min", "gt" for "max" and is used for the
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/// `cmpi` operation followed by the `select` operation:
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///
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/// %cond = cmpi "predicate" %v0, %v1
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/// %result = select %cond, %v0, %v1
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///
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/// Multiple values are scanned in a linear sequence. This creates a data
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/// dependences that wouldn't exist in a tree reduction, but is easier to
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/// recognize as a reduction by the subsequent passes.
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static Value buildMinMaxReductionSeq(Location loc, CmpIPredicate predicate,
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ValueRange values, OpBuilder &builder) {
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assert(!llvm::empty(values) && "empty min/max chain");
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auto valueIt = values.begin();
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Value value = *valueIt++;
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for (; valueIt != values.end(); ++valueIt) {
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auto cmpOp = builder.create<CmpIOp>(loc, predicate, value, *valueIt);
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value = builder.create<SelectOp>(loc, cmpOp.getResult(), value, *valueIt);
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}
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return value;
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}
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/// Emit instructions that correspond to computing the maximum value among the
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/// values of a (potentially) multi-output affine map applied to `operands`.
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static Value lowerAffineMapMax(OpBuilder &builder, Location loc, AffineMap map,
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ValueRange operands) {
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if (auto values = expandAffineMap(builder, loc, map, operands))
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return buildMinMaxReductionSeq(loc, CmpIPredicate::sgt, *values, builder);
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return nullptr;
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}
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/// Emit instructions that correspond to computing the minimum value among the
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/// values of a (potentially) multi-output affine map applied to `operands`.
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static Value lowerAffineMapMin(OpBuilder &builder, Location loc, AffineMap map,
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ValueRange operands) {
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if (auto values = expandAffineMap(builder, loc, map, operands))
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return buildMinMaxReductionSeq(loc, CmpIPredicate::slt, *values, builder);
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return nullptr;
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}
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/// Emit instructions that correspond to the affine map in the upper bound
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/// applied to the respective operands, and compute the minimum value across
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/// the results.
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Value mlir::lowerAffineUpperBound(AffineForOp op, OpBuilder &builder) {
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return lowerAffineMapMin(builder, op.getLoc(), op.getUpperBoundMap(),
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op.getUpperBoundOperands());
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}
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/// Emit instructions that correspond to the affine map in the lower bound
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/// applied to the respective operands, and compute the maximum value across
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/// the results.
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Value mlir::lowerAffineLowerBound(AffineForOp op, OpBuilder &builder) {
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return lowerAffineMapMax(builder, op.getLoc(), op.getLowerBoundMap(),
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op.getLowerBoundOperands());
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}
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namespace {
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class AffineMinLowering : public OpRewritePattern<AffineMinOp> {
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public:
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using OpRewritePattern<AffineMinOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(AffineMinOp op,
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PatternRewriter &rewriter) const override {
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Value reduced =
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lowerAffineMapMin(rewriter, op.getLoc(), op.map(), op.operands());
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if (!reduced)
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return failure();
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rewriter.replaceOp(op, reduced);
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return success();
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}
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};
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class AffineMaxLowering : public OpRewritePattern<AffineMaxOp> {
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public:
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using OpRewritePattern<AffineMaxOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(AffineMaxOp op,
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PatternRewriter &rewriter) const override {
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Value reduced =
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lowerAffineMapMax(rewriter, op.getLoc(), op.map(), op.operands());
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if (!reduced)
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return failure();
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rewriter.replaceOp(op, reduced);
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return success();
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}
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};
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/// Affine yields ops are removed.
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class AffineYieldOpLowering : public OpRewritePattern<AffineYieldOp> {
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public:
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using OpRewritePattern<AffineYieldOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(AffineYieldOp op,
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PatternRewriter &rewriter) const override {
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if (isa<scf::ParallelOp>(op->getParentOp())) {
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// scf.parallel does not yield any values via its terminator scf.yield but
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// models reductions differently using additional ops in its region.
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rewriter.replaceOpWithNewOp<scf::YieldOp>(op);
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return success();
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}
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rewriter.replaceOpWithNewOp<scf::YieldOp>(op, op.operands());
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return success();
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}
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};
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class AffineForLowering : public OpRewritePattern<AffineForOp> {
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public:
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using OpRewritePattern<AffineForOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(AffineForOp op,
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PatternRewriter &rewriter) const override {
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Location loc = op.getLoc();
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Value lowerBound = lowerAffineLowerBound(op, rewriter);
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Value upperBound = lowerAffineUpperBound(op, rewriter);
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Value step = rewriter.create<ConstantIndexOp>(loc, op.getStep());
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auto scfForOp = rewriter.create<scf::ForOp>(loc, lowerBound, upperBound,
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step, op.getIterOperands());
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rewriter.eraseBlock(scfForOp.getBody());
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rewriter.inlineRegionBefore(op.region(), scfForOp.region(),
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scfForOp.region().end());
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rewriter.replaceOp(op, scfForOp.results());
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return success();
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}
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};
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/// Returns the identity value associated with an AtomicRMWKind op.
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static Value getIdentityValue(AtomicRMWKind op, OpBuilder &builder,
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Location loc) {
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switch (op) {
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case AtomicRMWKind::addf:
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return builder.create<ConstantOp>(loc, builder.getF32FloatAttr(0));
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case AtomicRMWKind::addi:
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return builder.create<ConstantOp>(loc, builder.getI32IntegerAttr(0));
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case AtomicRMWKind::mulf:
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return builder.create<ConstantOp>(loc, builder.getF32FloatAttr(1));
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case AtomicRMWKind::muli:
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return builder.create<ConstantOp>(loc, builder.getI32IntegerAttr(1));
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// TODO: Add remaining reduction operations.
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default:
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(void)emitOptionalError(loc, "Reduction operation type not supported");
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break;
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}
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return nullptr;
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}
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/// Return the value obtained by applying the reduction operation kind
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/// associated with a binary AtomicRMWKind op to `lhs` and `rhs`.
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static Value getReductionOp(AtomicRMWKind op, OpBuilder &builder, Location loc,
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Value lhs, Value rhs) {
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switch (op) {
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case AtomicRMWKind::addf:
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return builder.create<AddFOp>(loc, lhs, rhs);
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case AtomicRMWKind::addi:
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return builder.create<AddIOp>(loc, lhs, rhs);
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case AtomicRMWKind::mulf:
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return builder.create<MulFOp>(loc, lhs, rhs);
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case AtomicRMWKind::muli:
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return builder.create<MulIOp>(loc, lhs, rhs);
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// TODO: Add remaining reduction operations.
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default:
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(void)emitOptionalError(loc, "Reduction operation type not supported");
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break;
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}
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return nullptr;
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}
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/// Convert an `affine.parallel` (loop nest) operation into a `scf.parallel`
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/// operation.
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class AffineParallelLowering : public OpRewritePattern<AffineParallelOp> {
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public:
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using OpRewritePattern<AffineParallelOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(AffineParallelOp op,
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PatternRewriter &rewriter) const override {
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Location loc = op.getLoc();
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SmallVector<Value, 8> steps;
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SmallVector<Value, 8> upperBoundTuple;
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SmallVector<Value, 8> lowerBoundTuple;
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SmallVector<Value, 8> identityVals;
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// Finding lower and upper bound by expanding the map expression.
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// Checking if expandAffineMap is not giving NULL.
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Optional<SmallVector<Value, 8>> lowerBound = expandAffineMap(
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rewriter, loc, op.lowerBoundsMap(), op.getLowerBoundsOperands());
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Optional<SmallVector<Value, 8>> upperBound = expandAffineMap(
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rewriter, loc, op.upperBoundsMap(), op.getUpperBoundsOperands());
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if (!lowerBound || !upperBound)
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return failure();
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upperBoundTuple = *upperBound;
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lowerBoundTuple = *lowerBound;
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steps.reserve(op.steps().size());
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for (Attribute step : op.steps())
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steps.push_back(rewriter.create<ConstantIndexOp>(
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loc, step.cast<IntegerAttr>().getInt()));
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// Get the terminator op.
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Operation *affineParOpTerminator = op.getBody()->getTerminator();
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scf::ParallelOp parOp;
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if (op.results().empty()) {
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// Case with no reduction operations/return values.
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parOp = rewriter.create<scf::ParallelOp>(loc, lowerBoundTuple,
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upperBoundTuple, steps,
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/*bodyBuilderFn=*/nullptr);
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rewriter.eraseBlock(parOp.getBody());
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rewriter.inlineRegionBefore(op.region(), parOp.region(),
|
|
parOp.region().end());
|
|
rewriter.replaceOp(op, parOp.results());
|
|
return success();
|
|
}
|
|
// Case with affine.parallel with reduction operations/return values.
|
|
// scf.parallel handles the reduction operation differently unlike
|
|
// affine.parallel.
|
|
ArrayRef<Attribute> reductions = op.reductions().getValue();
|
|
for (Attribute reduction : reductions) {
|
|
// For each of the reduction operations get the identity values for
|
|
// initialization of the result values.
|
|
Optional<AtomicRMWKind> reductionOp = symbolizeAtomicRMWKind(
|
|
static_cast<uint64_t>(reduction.cast<IntegerAttr>().getInt()));
|
|
assert(reductionOp.hasValue() &&
|
|
"Reduction operation cannot be of None Type");
|
|
AtomicRMWKind reductionOpValue = reductionOp.getValue();
|
|
identityVals.push_back(getIdentityValue(reductionOpValue, rewriter, loc));
|
|
}
|
|
parOp = rewriter.create<scf::ParallelOp>(
|
|
loc, lowerBoundTuple, upperBoundTuple, steps, identityVals,
|
|
/*bodyBuilderFn=*/nullptr);
|
|
|
|
// Copy the body of the affine.parallel op.
|
|
rewriter.eraseBlock(parOp.getBody());
|
|
rewriter.inlineRegionBefore(op.region(), parOp.region(),
|
|
parOp.region().end());
|
|
assert(reductions.size() == affineParOpTerminator->getNumOperands() &&
|
|
"Unequal number of reductions and operands.");
|
|
for (unsigned i = 0, end = reductions.size(); i < end; i++) {
|
|
// For each of the reduction operations get the respective mlir::Value.
|
|
Optional<AtomicRMWKind> reductionOp =
|
|
symbolizeAtomicRMWKind(reductions[i].cast<IntegerAttr>().getInt());
|
|
assert(reductionOp.hasValue() &&
|
|
"Reduction Operation cannot be of None Type");
|
|
AtomicRMWKind reductionOpValue = reductionOp.getValue();
|
|
rewriter.setInsertionPoint(&parOp.getBody()->back());
|
|
auto reduceOp = rewriter.create<scf::ReduceOp>(
|
|
loc, affineParOpTerminator->getOperand(i));
|
|
rewriter.setInsertionPointToEnd(&reduceOp.reductionOperator().front());
|
|
Value reductionResult =
|
|
getReductionOp(reductionOpValue, rewriter, loc,
|
|
reduceOp.reductionOperator().front().getArgument(0),
|
|
reduceOp.reductionOperator().front().getArgument(1));
|
|
rewriter.create<scf::ReduceReturnOp>(loc, reductionResult);
|
|
}
|
|
rewriter.replaceOp(op, parOp.results());
|
|
return success();
|
|
}
|
|
};
|
|
|
|
class AffineIfLowering : public OpRewritePattern<AffineIfOp> {
|
|
public:
|
|
using OpRewritePattern<AffineIfOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineIfOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
auto loc = op.getLoc();
|
|
|
|
// Now we just have to handle the condition logic.
|
|
auto integerSet = op.getIntegerSet();
|
|
Value zeroConstant = rewriter.create<ConstantIndexOp>(loc, 0);
|
|
SmallVector<Value, 8> operands(op.getOperands());
|
|
auto operandsRef = llvm::makeArrayRef(operands);
|
|
|
|
// Calculate cond as a conjunction without short-circuiting.
|
|
Value cond = nullptr;
|
|
for (unsigned i = 0, e = integerSet.getNumConstraints(); i < e; ++i) {
|
|
AffineExpr constraintExpr = integerSet.getConstraint(i);
|
|
bool isEquality = integerSet.isEq(i);
|
|
|
|
// Build and apply an affine expression
|
|
auto numDims = integerSet.getNumDims();
|
|
Value affResult = expandAffineExpr(rewriter, loc, constraintExpr,
|
|
operandsRef.take_front(numDims),
|
|
operandsRef.drop_front(numDims));
|
|
if (!affResult)
|
|
return failure();
|
|
auto pred = isEquality ? CmpIPredicate::eq : CmpIPredicate::sge;
|
|
Value cmpVal =
|
|
rewriter.create<CmpIOp>(loc, pred, affResult, zeroConstant);
|
|
cond =
|
|
cond ? rewriter.create<AndOp>(loc, cond, cmpVal).getResult() : cmpVal;
|
|
}
|
|
cond = cond ? cond
|
|
: rewriter.create<ConstantIntOp>(loc, /*value=*/1, /*width=*/1);
|
|
|
|
bool hasElseRegion = !op.elseRegion().empty();
|
|
auto ifOp = rewriter.create<scf::IfOp>(loc, cond, hasElseRegion);
|
|
rewriter.inlineRegionBefore(op.thenRegion(), &ifOp.thenRegion().back());
|
|
rewriter.eraseBlock(&ifOp.thenRegion().back());
|
|
if (hasElseRegion) {
|
|
rewriter.inlineRegionBefore(op.elseRegion(), &ifOp.elseRegion().back());
|
|
rewriter.eraseBlock(&ifOp.elseRegion().back());
|
|
}
|
|
|
|
// Ok, we're done!
|
|
rewriter.eraseOp(op);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Convert an "affine.apply" operation into a sequence of arithmetic
|
|
/// operations using the StandardOps dialect.
|
|
class AffineApplyLowering : public OpRewritePattern<AffineApplyOp> {
|
|
public:
|
|
using OpRewritePattern<AffineApplyOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineApplyOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
auto maybeExpandedMap =
|
|
expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(),
|
|
llvm::to_vector<8>(op.getOperands()));
|
|
if (!maybeExpandedMap)
|
|
return failure();
|
|
rewriter.replaceOp(op, *maybeExpandedMap);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Apply the affine map from an 'affine.load' operation to its operands, and
|
|
/// feed the results to a newly created 'std.load' operation (which replaces the
|
|
/// original 'affine.load').
|
|
class AffineLoadLowering : public OpRewritePattern<AffineLoadOp> {
|
|
public:
|
|
using OpRewritePattern<AffineLoadOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineLoadOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
// Expand affine map from 'affineLoadOp'.
|
|
SmallVector<Value, 8> indices(op.getMapOperands());
|
|
auto resultOperands =
|
|
expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
|
|
if (!resultOperands)
|
|
return failure();
|
|
|
|
// Build vector.load memref[expandedMap.results].
|
|
rewriter.replaceOpWithNewOp<mlir::LoadOp>(op, op.getMemRef(),
|
|
*resultOperands);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Apply the affine map from an 'affine.prefetch' operation to its operands,
|
|
/// and feed the results to a newly created 'std.prefetch' operation (which
|
|
/// replaces the original 'affine.prefetch').
|
|
class AffinePrefetchLowering : public OpRewritePattern<AffinePrefetchOp> {
|
|
public:
|
|
using OpRewritePattern<AffinePrefetchOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffinePrefetchOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
// Expand affine map from 'affinePrefetchOp'.
|
|
SmallVector<Value, 8> indices(op.getMapOperands());
|
|
auto resultOperands =
|
|
expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
|
|
if (!resultOperands)
|
|
return failure();
|
|
|
|
// Build std.prefetch memref[expandedMap.results].
|
|
rewriter.replaceOpWithNewOp<PrefetchOp>(op, op.memref(), *resultOperands,
|
|
op.isWrite(), op.localityHint(),
|
|
op.isDataCache());
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Apply the affine map from an 'affine.store' operation to its operands, and
|
|
/// feed the results to a newly created 'std.store' operation (which replaces
|
|
/// the original 'affine.store').
|
|
class AffineStoreLowering : public OpRewritePattern<AffineStoreOp> {
|
|
public:
|
|
using OpRewritePattern<AffineStoreOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineStoreOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
// Expand affine map from 'affineStoreOp'.
|
|
SmallVector<Value, 8> indices(op.getMapOperands());
|
|
auto maybeExpandedMap =
|
|
expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
|
|
if (!maybeExpandedMap)
|
|
return failure();
|
|
|
|
// Build std.store valueToStore, memref[expandedMap.results].
|
|
rewriter.replaceOpWithNewOp<mlir::StoreOp>(
|
|
op, op.getValueToStore(), op.getMemRef(), *maybeExpandedMap);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Apply the affine maps from an 'affine.dma_start' operation to each of their
|
|
/// respective map operands, and feed the results to a newly created
|
|
/// 'std.dma_start' operation (which replaces the original 'affine.dma_start').
|
|
class AffineDmaStartLowering : public OpRewritePattern<AffineDmaStartOp> {
|
|
public:
|
|
using OpRewritePattern<AffineDmaStartOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineDmaStartOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
SmallVector<Value, 8> operands(op.getOperands());
|
|
auto operandsRef = llvm::makeArrayRef(operands);
|
|
|
|
// Expand affine map for DMA source memref.
|
|
auto maybeExpandedSrcMap = expandAffineMap(
|
|
rewriter, op.getLoc(), op.getSrcMap(),
|
|
operandsRef.drop_front(op.getSrcMemRefOperandIndex() + 1));
|
|
if (!maybeExpandedSrcMap)
|
|
return failure();
|
|
// Expand affine map for DMA destination memref.
|
|
auto maybeExpandedDstMap = expandAffineMap(
|
|
rewriter, op.getLoc(), op.getDstMap(),
|
|
operandsRef.drop_front(op.getDstMemRefOperandIndex() + 1));
|
|
if (!maybeExpandedDstMap)
|
|
return failure();
|
|
// Expand affine map for DMA tag memref.
|
|
auto maybeExpandedTagMap = expandAffineMap(
|
|
rewriter, op.getLoc(), op.getTagMap(),
|
|
operandsRef.drop_front(op.getTagMemRefOperandIndex() + 1));
|
|
if (!maybeExpandedTagMap)
|
|
return failure();
|
|
|
|
// Build std.dma_start operation with affine map results.
|
|
rewriter.replaceOpWithNewOp<DmaStartOp>(
|
|
op, op.getSrcMemRef(), *maybeExpandedSrcMap, op.getDstMemRef(),
|
|
*maybeExpandedDstMap, op.getNumElements(), op.getTagMemRef(),
|
|
*maybeExpandedTagMap, op.getStride(), op.getNumElementsPerStride());
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Apply the affine map from an 'affine.dma_wait' operation tag memref,
|
|
/// and feed the results to a newly created 'std.dma_wait' operation (which
|
|
/// replaces the original 'affine.dma_wait').
|
|
class AffineDmaWaitLowering : public OpRewritePattern<AffineDmaWaitOp> {
|
|
public:
|
|
using OpRewritePattern<AffineDmaWaitOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineDmaWaitOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
// Expand affine map for DMA tag memref.
|
|
SmallVector<Value, 8> indices(op.getTagIndices());
|
|
auto maybeExpandedTagMap =
|
|
expandAffineMap(rewriter, op.getLoc(), op.getTagMap(), indices);
|
|
if (!maybeExpandedTagMap)
|
|
return failure();
|
|
|
|
// Build std.dma_wait operation with affine map results.
|
|
rewriter.replaceOpWithNewOp<DmaWaitOp>(
|
|
op, op.getTagMemRef(), *maybeExpandedTagMap, op.getNumElements());
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Apply the affine map from an 'affine.vector_load' operation to its operands,
|
|
/// and feed the results to a newly created 'vector.load' operation (which
|
|
/// replaces the original 'affine.vector_load').
|
|
class AffineVectorLoadLowering : public OpRewritePattern<AffineVectorLoadOp> {
|
|
public:
|
|
using OpRewritePattern<AffineVectorLoadOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineVectorLoadOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
// Expand affine map from 'affineVectorLoadOp'.
|
|
SmallVector<Value, 8> indices(op.getMapOperands());
|
|
auto resultOperands =
|
|
expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
|
|
if (!resultOperands)
|
|
return failure();
|
|
|
|
// Build vector.load memref[expandedMap.results].
|
|
rewriter.replaceOpWithNewOp<vector::LoadOp>(
|
|
op, op.getVectorType(), op.getMemRef(), *resultOperands);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Apply the affine map from an 'affine.vector_store' operation to its
|
|
/// operands, and feed the results to a newly created 'vector.store' operation
|
|
/// (which replaces the original 'affine.vector_store').
|
|
class AffineVectorStoreLowering : public OpRewritePattern<AffineVectorStoreOp> {
|
|
public:
|
|
using OpRewritePattern<AffineVectorStoreOp>::OpRewritePattern;
|
|
|
|
LogicalResult matchAndRewrite(AffineVectorStoreOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
// Expand affine map from 'affineVectorStoreOp'.
|
|
SmallVector<Value, 8> indices(op.getMapOperands());
|
|
auto maybeExpandedMap =
|
|
expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
|
|
if (!maybeExpandedMap)
|
|
return failure();
|
|
|
|
rewriter.replaceOpWithNewOp<vector::StoreOp>(
|
|
op, op.getValueToStore(), op.getMemRef(), *maybeExpandedMap);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
} // end namespace
|
|
|
|
void mlir::populateAffineToStdConversionPatterns(
|
|
OwningRewritePatternList &patterns, MLIRContext *ctx) {
|
|
// clang-format off
|
|
patterns.insert<
|
|
AffineApplyLowering,
|
|
AffineDmaStartLowering,
|
|
AffineDmaWaitLowering,
|
|
AffineLoadLowering,
|
|
AffineMinLowering,
|
|
AffineMaxLowering,
|
|
AffineParallelLowering,
|
|
AffinePrefetchLowering,
|
|
AffineStoreLowering,
|
|
AffineForLowering,
|
|
AffineIfLowering,
|
|
AffineYieldOpLowering>(ctx);
|
|
// clang-format on
|
|
}
|
|
|
|
void mlir::populateAffineToVectorConversionPatterns(
|
|
OwningRewritePatternList &patterns, MLIRContext *ctx) {
|
|
// clang-format off
|
|
patterns.insert<
|
|
AffineVectorLoadLowering,
|
|
AffineVectorStoreLowering>(ctx);
|
|
// clang-format on
|
|
}
|
|
|
|
namespace {
|
|
class LowerAffinePass : public ConvertAffineToStandardBase<LowerAffinePass> {
|
|
void runOnOperation() override {
|
|
OwningRewritePatternList patterns;
|
|
populateAffineToStdConversionPatterns(patterns, &getContext());
|
|
populateAffineToVectorConversionPatterns(patterns, &getContext());
|
|
ConversionTarget target(getContext());
|
|
target
|
|
.addLegalDialect<scf::SCFDialect, StandardOpsDialect, VectorDialect>();
|
|
if (failed(applyPartialConversion(getOperation(), target,
|
|
std::move(patterns))))
|
|
signalPassFailure();
|
|
}
|
|
};
|
|
} // namespace
|
|
|
|
/// Lowers If and For operations within a function into their lower level CFG
|
|
/// equivalent blocks.
|
|
std::unique_ptr<Pass> mlir::createLowerAffinePass() {
|
|
return std::make_unique<LowerAffinePass>();
|
|
}
|