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llvm-project/llvm/test/CodeGen
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David Green a10789d6cd [ARM] Recognize SSAT and USAT from SMIN/SMAX 
We have some recognition of SSAT and USAT from SELECT_CC at the moment.
This extends the matching to SMIN/SMAX which can help catch more cases,
either from min/max being the canonical form in instcombine or from some
expanded nodes like fp_to_si_sat.

Differential Revision: https://reviews.llvm.org/D119819
2022-02-23 08:55:54 +00:00
..
AArch64
Revert "Revert "[AArch64][GlobalISel] Optimize conjunctions of compares to conditional compares.""
2022-02-22 17:22:11 -08:00
AMDGPU
[AMDGPU] Pre-commit load/store combine tests. NFC.
2022-02-22 16:28:44 -08:00
ARC
…
ARM
[ARM] Recognize SSAT and USAT from SMIN/SMAX
2022-02-23 08:55:54 +00:00
AVR
[AVR] Fix a potential assert failure
2022-02-11 02:25:58 +00:00
BPF
[BPF] Fix a BTF type pruning bug
2022-02-16 17:23:34 -08:00
CSKY
[CSKY] Add inline asm constraints and related codegen support
2022-02-07 17:45:37 +08:00
Generic
[CodeGen][test] XFAIL CodeGen/Generic/ForceStackAlign.ll on SPARC
2022-02-08 08:57:59 +01:00
Hexagon
[Hexagon] Fix operation actions for v128f16
2022-02-08 15:28:37 -08:00
Inputs
…
Lanai
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LoongArch
[LoongArch] Fix atomic instructions operands sequence
2022-02-19 09:22:10 +08:00
M68k
m68k: Support bit shifts on 64-bit integers
2022-02-12 06:11:49 +08:00
Mips
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MIR
MIR: Start diagnosing too many operands on an instruction
2022-02-21 10:36:39 -05:00
MLRegalloc
[NFC] Fixing test requirements I broke
2022-02-09 09:11:34 -06:00
MSP430
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NVPTX
[NVPTX] Fix NVPTXReplaceImageHandles for multiple uses of a texref
2022-02-15 01:30:13 +03:00
PowerPC
[SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
2022-02-20 21:11:23 -08:00
RISCV
[RISCV] Add more test for GORCI aliaes in Zbp extension
2022-02-23 08:02:33 +00:00
SPARC
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SystemZ
[SystemZ/z/OS] Add va intrinsics for XPLINK
2022-02-22 14:35:05 -05:00
Thumb
[SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
2022-02-20 21:11:23 -08:00
Thumb2
[SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
2022-02-20 21:11:23 -08:00
VE
[VE] Split unsupported v512.32 ops
2022-02-22 14:29:41 +01:00
WebAssembly
[SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
2022-02-20 21:11:23 -08:00
WinCFGuard
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WinEH
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X86
Encode address offsets of basic blocks relative to the end of the previous basic blocks.
2022-02-22 15:46:46 -08:00
XCore
[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
2022-02-18 16:10:56 +00:00