e13e95bc44
Do optimization to turn x >> (shift & 31/63) into a single srlv instead of andi + srlv, since the mips variable shift instruction already implicitly masks the shift, like x86, wasm and AMDGPU. Copy the X86DAGToDAGISel::isUnneededShiftMask() function to MIPS for checking whether need combine two instructions to one.
85 lines
2.1 KiB
LLVM
85 lines
2.1 KiB
LLVM
; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu | FileCheck %s --check-prefixes=MIPS32
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; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
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; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
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define i32 @shl_32(i32 %a, i32 %b) {
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; MIPS32-LABLE: shl_32:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: sllv $2, $4, $5
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; MIPS64-LABLE: shl_32:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: sll $1, $5, 0
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; MIPS64-NEXT: sll $2, $4, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: sllv $2, $2, $1
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%_1 = and i32 %b, 31
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%_0 = shl i32 %a, %_1
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ret i32 %_0
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}
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define i32 @lshr_32(i32 %a, i32 %b) {
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; MIPS32-LABLE: lshr_32:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: srlv $2, $4, $5
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; MIPS64-LABLE: lshr_32:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: sll $1, $5, 0
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; MIPS64-NEXT: sll $2, $4, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: srlv $2, $2, $1
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%_1 = and i32 %b, 31
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%_0 = lshr i32 %a, %_1
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ret i32 %_0
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}
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define i32 @ashr_32(i32 %a, i32 %b) {
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; MIPS32-LABLE: ashr_32:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: srav $2, $4, $5
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; MIPS64-LABLE: ashr_32:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: sll $1, $5, 0
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; MIPS64-NEXT: sll $2, $4, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: srav $2, $2, $1
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%_1 = and i32 %b, 31
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%_0 = ashr i32 %a, %_1
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ret i32 %_0
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}
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define i64 @shl_64(i64 %a, i64 %b) {
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; MIPS64-LABLE: shl_64:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: sll $1, $5, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: dsllv $2, $4, $1
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%_1 = and i64 %b, 63
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%_0 = shl i64 %a, %_1
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ret i64 %_0
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}
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define i64 @lshr_64(i64 %a, i64 %b) {
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; MIPS64-LABLE: lshr_64:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: sll $1, $5, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: dsrlv $2, $4, $1
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%_1 = and i64 %b, 63
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%_0 = lshr i64 %a, %_1
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ret i64 %_0
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}
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define i64 @ashr_64(i64 %a, i64 %b) {
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; MIPS64-LABLE: ashr_64:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: sll $1, $5, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: dsrav $2, $4, $1
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%_1 = and i64 %b, 63
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%_0 = ashr i64 %a, %_1
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ret i64 %_0
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}
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