a44c15874d
Propagate demanded bits through readfirstlane intrinsic in AMDGPUISelLowering with SimplifyDemandedBitsForTargetNode implementation. This allows upstream zero/sign extensions to be eliminated when only a subset of bits is used after the intrinsic. Partially addresses #128390.
61 lines
2.3 KiB
LLVM
61 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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define void @readfirstlane_demanded_i8_zext_store(i8 %src, ptr addrspace(1) %ptr) {
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; GCN-LABEL: readfirstlane_demanded_i8_zext_store:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s4, v0
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: global_store_byte v[1:2], v0, off
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%zext = zext i8 %src to i32
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %zext)
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%trunc = trunc i32 %readfirstlane to i8
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store i8 %trunc, ptr addrspace(1) %ptr
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ret void
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}
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define void @readfirstlane_demanded_i8_sext_store(i8 %src, ptr addrspace(1) %ptr) {
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; GCN-LABEL: readfirstlane_demanded_i8_sext_store:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s4, v0
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: global_store_byte v[1:2], v0, off
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%sext = sext i8 %src to i32
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %sext)
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%trunc = trunc i32 %readfirstlane to i8
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store i8 %trunc, ptr addrspace(1) %ptr
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ret void
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}
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define i16 @readfirstlane_demanded_i16_zext(i16 %src) {
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; GCN-LABEL: readfirstlane_demanded_i16_zext:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s4, v0
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%zext = zext i16 %src to i32
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %zext)
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%trunc = trunc i32 %readfirstlane to i16
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ret i16 %trunc
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}
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define i16 @readfirstlane_demanded_i16_sext(i16 %src) {
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; GCN-LABEL: readfirstlane_demanded_i16_sext:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s4, v0
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%sext = sext i16 %src to i32
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %sext)
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%trunc = trunc i32 %readfirstlane to i16
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ret i16 %trunc
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}
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