a44c15874d
Propagate demanded bits through readfirstlane intrinsic in AMDGPUISelLowering with SimplifyDemandedBitsForTargetNode implementation. This allows upstream zero/sign extensions to be eliminated when only a subset of bits is used after the intrinsic. Partially addresses #128390.
31 lines
1.1 KiB
LLVM
31 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s
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define amdgpu_gs i32 @main() {
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; CHECK-LABEL: main:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_mov_b32 s0, 0
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
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; CHECK-NEXT: s_bitcmp1_b32 s0, 0
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; CHECK-NEXT: s_cselect_b32 s0, -1, 0
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; CHECK-NEXT: s_xor_b32 s0, s0, -1
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: s_wait_alu depctr_va_sdst(0)
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; CHECK-NEXT: ; return to shader part epilog
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bb:
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%i = call i1 @llvm.amdgcn.readfirstlane.i1(i1 false)
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br label %bb1
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bb1:
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%i2 = zext i1 %i to i32
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%i3 = call i32 @llvm.amdgcn.wwm.i32(i32 0)
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%i4 = call i32 @llvm.amdgcn.wwm.i32(i32 %i2)
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%i5 = trunc i32 %i4 to i1
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%i6 = trunc i32 %i3 to i1
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%i7 = or i1 %i6, %i5
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%i8 = select i1 %i7, i32 0, i32 1
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ret i32 %i8
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}
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