Vincent Lejeune a4d8d2ef2b R600: Fix wrong export reswizzling ...

llvm-svn: 185941

2013-07-09 15:03:19 +00:00

..

AArch64

AArch64: correct CodeGen of MOVZ/MOVK combinations.

2013-07-01 19:23:10 +00:00

ARM

Add a comment to this change, requested by Eric Christopher.

2013-07-08 19:52:51 +00:00

CPP

test commit: remove blank line.

2013-03-14 05:43:59 +00:00

Generic

Debug Info: clean up usage of Verify.

2013-06-28 05:43:10 +00:00

Hexagon

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Inputs

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

MBlaze

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

Mips

[mips] Fix test case to check that mips64 instructions are generated.

2013-07-01 20:18:58 +00:00

MSP430

Really fix the test. Sorry for the breakage...

2013-07-01 19:51:36 +00:00

NVPTX

[NVPTX] Add support for module-scope inline asm

2013-07-01 13:00:14 +00:00

PowerPC

PPC: Allocate RS spill slot for unaligned i64 load/store

2013-07-09 06:34:51 +00:00

R600

R600: Fix wrong export reswizzling

2013-07-09 15:03:19 +00:00

SI

Add R600 backend

2012-12-11 21:25:42 +00:00

SPARC

Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.

2013-06-17 19:00:36 +00:00

SystemZ

[SystemZ] Use MVC for simple load/store pairs

2013-07-09 09:46:39 +00:00

Thumb

LocalStackSlotAllocation improvements

2013-04-30 20:04:37 +00:00

Thumb2

ARM: allow predicated barriers in Thumb mode

2013-06-26 16:52:32 +00:00

X86

Revert r185872 - "Stop emitting weak symbols into the "coal" sections"

2013-07-09 10:00:16 +00:00

XCore

[XCore] Add ISel pattern for LDWCP

2013-07-03 07:48:50 +00:00