bdb5e4e4ca
This crash was introduced in r358032 as we try to construct an EVT from an MVT in order to find the register type for the calling conv. Fall back instead of trying to do this with an invalid MVT coming from i256. llvm-svn: 358314
224 lines
8.6 KiB
C++
224 lines
8.6 KiB
C++
//===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements some simple delegations needed for call lowering.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Module.h"
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#define DEBUG_TYPE "call-lowering"
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using namespace llvm;
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void CallLowering::anchor() {}
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bool CallLowering::lowerCall(
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MachineIRBuilder &MIRBuilder, ImmutableCallSite CS, unsigned ResReg,
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ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const {
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auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();
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// First step is to marshall all the function's parameters into the correct
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// physregs and memory locations. Gather the sequence of argument types that
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// we'll pass to the assigner function.
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SmallVector<ArgInfo, 8> OrigArgs;
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unsigned i = 0;
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unsigned NumFixedArgs = CS.getFunctionType()->getNumParams();
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for (auto &Arg : CS.args()) {
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ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{},
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i < NumFixedArgs};
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setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CS);
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// We don't currently support swifterror or swiftself args.
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if (OrigArg.Flags.isSwiftError() || OrigArg.Flags.isSwiftSelf())
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return false;
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OrigArgs.push_back(OrigArg);
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++i;
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}
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MachineOperand Callee = MachineOperand::CreateImm(0);
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if (const Function *F = CS.getCalledFunction())
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Callee = MachineOperand::CreateGA(F, 0);
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else
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Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
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ArgInfo OrigRet{ResReg, CS.getType(), ISD::ArgFlagsTy{}};
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if (!OrigRet.Ty->isVoidTy())
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setArgFlags(OrigRet, AttributeList::ReturnIndex, DL, CS);
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return lowerCall(MIRBuilder, CS.getCallingConv(), Callee, OrigRet, OrigArgs);
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}
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template <typename FuncInfoTy>
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void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
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const DataLayout &DL,
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const FuncInfoTy &FuncInfo) const {
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const AttributeList &Attrs = FuncInfo.getAttributes();
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if (Attrs.hasAttribute(OpIdx, Attribute::ZExt))
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Arg.Flags.setZExt();
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if (Attrs.hasAttribute(OpIdx, Attribute::SExt))
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Arg.Flags.setSExt();
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if (Attrs.hasAttribute(OpIdx, Attribute::InReg))
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Arg.Flags.setInReg();
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if (Attrs.hasAttribute(OpIdx, Attribute::StructRet))
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Arg.Flags.setSRet();
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if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf))
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Arg.Flags.setSwiftSelf();
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if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError))
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Arg.Flags.setSwiftError();
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if (Attrs.hasAttribute(OpIdx, Attribute::ByVal))
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Arg.Flags.setByVal();
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if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca))
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Arg.Flags.setInAlloca();
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if (Arg.Flags.isByVal() || Arg.Flags.isInAlloca()) {
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Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType();
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Arg.Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
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// For ByVal, alignment should be passed from FE. BE will guess if
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// this info is not there but there are cases it cannot get right.
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unsigned FrameAlign;
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if (FuncInfo.getParamAlignment(OpIdx - 2))
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FrameAlign = FuncInfo.getParamAlignment(OpIdx - 2);
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else
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FrameAlign = getTLI()->getByValTypeAlignment(ElementTy, DL);
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Arg.Flags.setByValAlign(FrameAlign);
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}
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if (Attrs.hasAttribute(OpIdx, Attribute::Nest))
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Arg.Flags.setNest();
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Arg.Flags.setOrigAlign(DL.getABITypeAlignment(Arg.Ty));
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}
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template void
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CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
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const DataLayout &DL,
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const Function &FuncInfo) const;
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template void
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CallLowering::setArgFlags<CallInst>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
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const DataLayout &DL,
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const CallInst &FuncInfo) const;
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bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
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ArrayRef<ArgInfo> Args,
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ValueHandler &Handler) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const DataLayout &DL = F.getParent()->getDataLayout();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
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unsigned NumArgs = Args.size();
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for (unsigned i = 0; i != NumArgs; ++i) {
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MVT CurVT = MVT::getVT(Args[i].Ty);
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if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo)) {
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// Try to use the register type if we couldn't assign the VT.
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if (!Handler.isArgumentHandler() || !CurVT.isValid())
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return false;
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CurVT = TLI->getRegisterTypeForCallingConv(
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F.getContext(), F.getCallingConv(), EVT(CurVT));
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if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo))
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return false;
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}
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}
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for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {
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assert(j < ArgLocs.size() && "Skipped too many arg locs");
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CCValAssign &VA = ArgLocs[j];
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assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
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if (VA.needsCustom()) {
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j += Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));
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continue;
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}
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if (VA.isRegLoc()) {
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MVT OrigVT = MVT::getVT(Args[i].Ty);
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MVT VAVT = VA.getValVT();
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if (Handler.isArgumentHandler() && VAVT != OrigVT) {
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if (VAVT.getSizeInBits() < OrigVT.getSizeInBits())
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return false; // Can't handle this type of arg yet.
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const LLT VATy(VAVT);
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unsigned NewReg =
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MIRBuilder.getMRI()->createGenericVirtualRegister(VATy);
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Handler.assignValueToReg(NewReg, VA.getLocReg(), VA);
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// If it's a vector type, we either need to truncate the elements
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// or do an unmerge to get the lower block of elements.
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if (VATy.isVector() &&
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VATy.getNumElements() > OrigVT.getVectorNumElements()) {
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const LLT OrigTy(OrigVT);
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// Just handle the case where the VA type is 2 * original type.
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if (VATy.getNumElements() != OrigVT.getVectorNumElements() * 2) {
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LLVM_DEBUG(dbgs()
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<< "Incoming promoted vector arg has too many elts");
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return false;
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}
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auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg});
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MIRBuilder.buildCopy(Args[i].Reg, Unmerge.getReg(0));
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} else {
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MIRBuilder.buildTrunc(Args[i].Reg, {NewReg}).getReg(0);
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}
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} else {
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Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA);
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}
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} else if (VA.isMemLoc()) {
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MVT VT = MVT::getVT(Args[i].Ty);
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unsigned Size = VT == MVT::iPTR ? DL.getPointerSize()
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: alignTo(VT.getSizeInBits(), 8) / 8;
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unsigned Offset = VA.getLocMemOffset();
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MachinePointerInfo MPO;
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unsigned StackAddr = Handler.getStackAddress(Size, Offset, MPO);
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Handler.assignValueToAddress(Args[i].Reg, StackAddr, Size, MPO, VA);
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} else {
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// FIXME: Support byvals and other weirdness
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return false;
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}
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}
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return true;
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}
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unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg,
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CCValAssign &VA) {
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LLT LocTy{VA.getLocVT()};
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if (LocTy.getSizeInBits() == MRI.getType(ValReg).getSizeInBits())
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return ValReg;
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switch (VA.getLocInfo()) {
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default: break;
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case CCValAssign::Full:
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case CCValAssign::BCvt:
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// FIXME: bitconverting between vector types may or may not be a
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// nop in big-endian situations.
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return ValReg;
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case CCValAssign::AExt: {
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auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
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return MIB->getOperand(0).getReg();
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}
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case CCValAssign::SExt: {
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unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildSExt(NewReg, ValReg);
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return NewReg;
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}
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case CCValAssign::ZExt: {
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unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildZExt(NewReg, ValReg);
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return NewReg;
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}
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}
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llvm_unreachable("unable to extend register");
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}
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void CallLowering::ValueHandler::anchor() {}
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