3ac9fe69f7
This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register count to 16(x0-x16). * The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits. `RVE` can be combined with all current standard extensions. The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are: * Only 6 integer argument registers (rather than 8). * Only 2 callee-saved registers (rather than 12). * A Stack Alignment of 32bits (rather than 128bits). * ilp32e isn't compatible with D ISA extension. If `ilp32e` or `lp64` is used with an ISA that has any of the registers x16-x31 and f0-f31, then these registers are considered temporaries. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment\ to 4-bytes for types with length of 2*XLEN. FastCC is also supported on RVE, while GHC isn't since there is only one avaiable register. Differential Revision: https://reviews.llvm.org/D70401
90 lines
3.6 KiB
C++
90 lines
3.6 KiB
C++
//===-- RISCVFrameLowering.h - Define frame lowering for RISC-V -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class implements RISC-V specific bits of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
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#define LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/Support/TypeSize.h"
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namespace llvm {
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class RISCVSubtarget;
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class RISCVFrameLowering : public TargetFrameLowering {
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public:
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explicit RISCVFrameLowering(const RISCVSubtarget &STI);
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const;
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StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS) const override;
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bool hasFP(const MachineFunction &MF) const override;
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bool hasBP(const MachineFunction &MF) const;
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bool hasReservedCallFrame(const MachineFunction &MF) const override;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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// Get the first stack adjustment amount for SplitSPAdjust.
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// Return 0 if we don't want to split the SP adjustment in prologue and
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// epilogue.
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uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const;
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bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
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bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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bool isSupportedStackID(TargetStackID::Value ID) const override;
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TargetStackID::Value getStackIDForScalableVectors() const override;
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bool isStackIdSafeForLocalArea(unsigned StackId) const override {
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// We don't support putting RISC-V Vector objects into the pre-allocated
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// local frame block at the moment.
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return StackId != TargetStackID::ScalableVector;
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}
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protected:
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const RISCVSubtarget &STI;
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private:
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void determineFrameLayout(MachineFunction &MF) const;
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void adjustStackForRVV(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
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int64_t Amount, MachineInstr::MIFlag Flag) const;
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std::pair<int64_t, Align>
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assignRVVStackObjectOffsets(MachineFunction &MF) const;
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};
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} // namespace llvm
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#endif
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