Lu Weining 78abc45c44

[LoongArch] Improve codegen for atomic cmpxchg ops (#69339) ...

PR #67391 improved atomic codegen by handling memory ordering specified
by the `cmpxchg` instruction. An acquire barrier needs to be generated
when memory ordering includes an acquire operation. This PR improves the
codegen further by only handling the failure ordering.

2023-10-19 09:21:51 +08:00

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add.ll

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and.ll

[LoongArch] Optimize (and (a & ~((2^^X - 1) << Y)) to (bstrins a, zero, X+Y-1, Y)

2023-08-28 08:36:54 +08:00

ashr.ll

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atomic-cmpxchg.ll

[LoongArch] Improve codegen for atomic cmpxchg ops (#69339)

2023-10-19 09:21:51 +08:00

atomicrmw-fp.ll

[LoongArch] Support finer-grained DBAR hints for LA664+ (#68787)

2023-10-12 15:04:51 +08:00

atomicrmw-minmax.ll

[LoongArch] Add some atomic tests (#68766)

2023-10-11 18:28:04 +08:00

atomicrmw.ll

[LoongArch] Add some atomic tests (#68766)

2023-10-11 18:28:04 +08:00

br.ll

[LoongArch] Implement isSExtCheaperThanZExt

2023-07-25 09:41:32 +08:00

call.ll

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double-convert.ll

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fadd.ll

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fcmp-dbl.ll

[LoongArch] Explicitly specify instruction properties

2023-07-11 08:45:24 +08:00

fcmp-flt.ll

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fdiv.ll

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fence-singlethread.ll

[LoongArch] Support finer-grained DBAR hints for LA664+ (#68787)

2023-10-12 15:04:51 +08:00

fence.ll

[LoongArch] Support finer-grained DBAR hints for LA664+ (#68787)

2023-10-12 15:04:51 +08:00

float-convert.ll

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fmul.ll

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fneg.ll

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fsub.ll

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icmp.ll

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indirectbr.ll

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load-store-atomic.ll

[LoongArch] Support finer-grained DBAR hints for LA664+ (#68787)

2023-10-12 15:04:51 +08:00

load-store-fp.ll

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load-store.ll

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lshr.ll

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mul.ll

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or.ll

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sdiv-udiv-srem-urem.ll

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select-bare-dbl.ll

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select-bare-flt.ll

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select-bare-int.ll

[LoongArch] Optimize conditional selection of integer

2023-06-26 10:33:51 +08:00

select-fpcc-dbl.ll

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select-fpcc-flt.ll

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select-fpcc-int.ll

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select-icc-dbl.ll

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select-icc-flt.ll

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select-icc-int.ll

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sext-zext-trunc.ll

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shl.ll

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sub.ll

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xor.ll

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