shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/tools/llvm-mca/RISCV
History
Michael Maitland a8cb4f7273 [RISCV][llvm-mca] Fix failing strided-load-x0.s test 
58f1640635feff282935153d295dfb4ea1818401 was committed but had a broken
test that I did not add the updated version to the commit. This patch
fixes the test.
2024-01-04 12:59:31 -08:00
..
SiFive7
[RISCV][llvm-mca] Fix failing strided-load-x0.s test
2024-01-04 12:59:31 -08:00
different-lmul-instruments.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
different-sew-instruments.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
disable-im.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
fractional-lmul-data.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
lit.local.cfg
[RISCV][llvm-mca] Add mca tests for riscv lmul instruments
2023-05-22 10:36:42 -07:00
lmul-instrument-at-start.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
lmul-instrument-in-middle.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
lmul-instrument-in-region.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
lmul-instrument-straddles-region.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
multiple-same-lmul-instruments.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
multiple-same-sew-instruments.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
needs-sew-but-only-lmul.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
no-vsetvli-to-start.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
riscv-lmul-instrument-no-data-is-err.s
[llvm-mca][RISCV] Add RISCV-SEW instrument
2023-07-14 12:12:04 -07:00
riscv-sew-instrument-no-data-is-err.s
[llvm-mca][RISCV] Add RISCV-SEW instrument
2023-07-14 12:12:04 -07:00
sew-instrument-at-start.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
sew-instrument-in-middle.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
sew-instrument-in-region.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
sew-instrument-straddles-region.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
unknown-instrument-is-err.s
[RISCV][llvm-mca] Add mca tests for riscv lmul instruments
2023-05-22 10:36:42 -07:00
unknown-lmul-is-err.s
[llvm-mca][RISCV] Add RISCV-SEW instrument
2023-07-14 12:12:04 -07:00
unknown-sew-is-err.s
[llvm-mca][RISCV] Add RISCV-SEW instrument
2023-07-14 12:12:04 -07:00
vle-vse.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
vsetivli-lmul-instrument.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
vsetivli-lmul-sew-instrument.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
vsetvli-lmul-instrument.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
vsetvli-lmul-sew-instrument.s
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00