b8cbc5c02c
The KernelEnvironment is for compile time information about a kernel. It allows the compiler to feed information to the runtime. The KernelLaunchEnvironment is for dynamic information *per* kernel launch. It allows the rutime to feed information to the kernel that is not shared with other invocations of the kernel. The first use case is to replace the globals that synchronize teams reductions with per-launch versions. This allows concurrent teams reductions. More uses cases will follow, e.g., per launch memory pools. Fixes: https://github.com/llvm/llvm-project/issues/70249
59 lines
2.7 KiB
C++
59 lines
2.7 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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#pragma omp target teams ompx_bare
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{
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a = 2;
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}
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return a;
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}
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int bar(int n){
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int a = 0;
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a += ftemplate<char>(n);
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return a;
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}
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#endif
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// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l13
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// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
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// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
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// CHECK-NEXT: store i8 [[TMP0]], ptr [[A_CASTED]], align 1
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
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// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
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// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l13_omp_outlined(ptr null, ptr [[DOTZERO_ADDR]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
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// CHECK-NEXT: ret void
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//
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//
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// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l13_omp_outlined
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// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
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// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
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// CHECK-NEXT: store i8 2, ptr [[A_ADDR]], align 1
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// CHECK-NEXT: ret void
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//
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