368972c3b3
Summary: The post-RA scheduler occasionally uses additional implicit operands when the vector implicit operand as a whole is killed, but some subregisters are still live because they are directly referenced later. Unfortunately, this seems incredibly subtle to reproduce. Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test and others. Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25656 llvm-svn: 285835
32 lines
1.2 KiB
YAML
32 lines
1.2 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s
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# This tests a situation where a sub-register of a killed super-register operand
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# of V_MOVRELS happens to have an undef use later on. This leads to the post RA
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# scheduler adding additional implicit operands to the V_MOVRELS, which used
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# to fail machine instruction verification.
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--- |
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define amdgpu_vs void @main(i32 %arg) { ret void }
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...
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---
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# CHECK-LABEL: name: main
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# CHECK-LABEL: bb.0:
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# CHECK: V_MOVRELS_B32_e32
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# CHECK: V_MAC_F32_e32
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name: main
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tracksRegLiveness: true
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body: |
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bb.0:
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%m0 = S_MOV_B32 undef %sgpr0
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V_MOVRELD_B32_e32 undef %vgpr2, 0, implicit %m0, implicit %exec, implicit-def %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)
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%m0 = S_MOV_B32 undef %sgpr0
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%vgpr1 = V_MOVRELS_B32_e32 undef %vgpr1, implicit %m0, implicit %exec, implicit killed %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
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%vgpr4 = V_MAC_F32_e32 undef %vgpr0, undef %vgpr0, undef %vgpr4, implicit %exec
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EXP 15, 12, 0, 1, 0, undef %vgpr0, killed %vgpr1, killed %vgpr4, undef %vgpr0, implicit %exec
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S_ENDPGM
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...
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