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History

Matthias Braun de5fea2c30 MIRParser: Allow regclass specification on operand

You can now define the register class of a virtual register on the
operand itself avoiding the need to use a "registers:" block.

Example: "%0:gr64 = COPY %rax"

Differential Revision: https://reviews.llvm.org/D22398

llvm-svn: 292321

2017-01-18 00:59:19 +00:00

cfi-def-cfa.mir

MIRParser: Use shorter cfi identifiers

2016-07-26 18:20:00 +00:00

expected-target-flag-name.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

generic-virtual-registers-error.mir

[GlobalISel] More fix for the size vs. type typo. NFC.

2016-12-22 22:50:34 +00:00

generic-virtual-registers-with-regbank-error.mir

[GlobalISel] More fix for the size vs. type typo. NFC.

2016-12-22 22:50:34 +00:00

intrinsics.mir

CodeGen: add new "intrinsic" MachineOperand kind.

2016-07-29 20:32:59 +00:00

invalid-target-flag-name.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

lit.local.cfg

…

multiple-lhs-operands.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

MIRParser: Allow regclass specification on operand

2017-01-18 00:59:19 +00:00

spill-fold.mir

[AArch64] Fold some filled/spilled subreg COPYs

2017-01-05 21:51:42 +00:00

stack-object-local-offset.mir

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

target-flags.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00