44d122188e
Previously they were legal by default, so the truncstore/extload test cases would get combined and crash during selection. These are set to expand for f16 so do the same for bf16.
72 lines
2.2 KiB
LLVM
72 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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define <vscale x 1 x bfloat> @load_nxv1bf16(ptr %p) {
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; CHECK-LABEL: load_nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: ret
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%x = load <vscale x 1 x bfloat>, ptr %p
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ret <vscale x 1 x bfloat> %x
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}
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define <vscale x 2 x bfloat> @load_nxv2bf16(ptr %p) {
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; CHECK-LABEL: load_nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: ret
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%x = load <vscale x 2 x bfloat>, ptr %p
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ret <vscale x 2 x bfloat> %x
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}
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define <vscale x 4 x bfloat> @load_nxv4bf16(ptr %p) {
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; CHECK-LABEL: load_nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl1re16.v v8, (a0)
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; CHECK-NEXT: ret
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%x = load <vscale x 4 x bfloat>, ptr %p
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ret <vscale x 4 x bfloat> %x
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}
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define <vscale x 8 x bfloat> @load_nxv8bf16(ptr %p) {
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; CHECK-LABEL: load_nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl2re16.v v8, (a0)
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; CHECK-NEXT: ret
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%x = load <vscale x 8 x bfloat>, ptr %p
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ret <vscale x 8 x bfloat> %x
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}
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define <vscale x 16 x bfloat> @load_nxv16bf16(ptr %p) {
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; CHECK-LABEL: load_nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl4re16.v v8, (a0)
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; CHECK-NEXT: ret
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%x = load <vscale x 16 x bfloat>, ptr %p
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ret <vscale x 16 x bfloat> %x
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}
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define <vscale x 32 x bfloat> @load_nxv32bf16(ptr %p) {
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; CHECK-LABEL: load_nxv32bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl8re16.v v8, (a0)
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; CHECK-NEXT: ret
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%x = load <vscale x 32 x bfloat>, ptr %p
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ret <vscale x 32 x bfloat> %x
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}
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define <vscale x 4 x float> @extload(ptr %p) {
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; CHECK-LABEL: extload:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl1re16.v v10, (a0)
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
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; CHECK-NEXT: ret
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%x = load <vscale x 4 x bfloat>, ptr %p
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%y = fpext <vscale x 4 x bfloat> %x to <vscale x 4 x float>
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ret <vscale x 4 x float> %y
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}
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