22f98740b6
This patch handles target lowering and calling convention. For target lowering, the vector tuple type represented as multiple scalable vectors is now changed to a single `MVT`, each `MVT` has a corresponding register class. The load/store of vector tuples are handled as the same way but need another vector insert/extract instructions to get sub-register group. Inline assembly constraint for vector tuple type can directly be modeled as "vr" which is identical to normal vector registers. For calling convention, it no longer needs an alternative algorithm to handle register allocation, this makes the code easier to maintain and read. Stacked on https://github.com/llvm/llvm-project/pull/97994
19 lines
982 B
LLVM
19 lines
982 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+m \
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; RUN: -regalloc=fast -verify-machineinstrs < %s | FileCheck %s
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; This test previously crashed with an error "ran out of registers during register allocation"
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declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 16 x i1>, i32, i32)
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define void @test_vsseg2_mask_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl) {
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; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
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; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
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ret void
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}
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